Tri-Gate Orthogonal Channel Transistor for Tunnel-Free Nonvolatile Memory
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Solution Overview
Problem
Flash memory devices suffer from performance degradation over time due to cumulative damage to the tunneling dielectric, leading to a need for a nonvolatile memory device with longer endurance.
Innovation Solution
A semiconductor device utilizing a metal oxide semiconductor channel layer with three gate electrodes and dual semiconductor channels, providing both horizontal and vertical electrical current paths, which stores electrical charges without charge tunneling, thus enhancing reliability and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory devices use charge tunneling for nonvolatile storage, then data retention is achieved, but device performance degrades over time due to cumulative damage to the tunneling dielectric
Solution Approach 1:
The patent extracts and eliminates the charge tunneling mechanism from the memory device. By using a different charge storage mechanism (trapped charges in the oxide layer rather than tunneling through it), the harmful tunneling dielectric damage is removed while maintaining nonvolatile data retention capability
Solution Approach 2:
The patent changes the fundamental operating parameter from charge tunneling to charge trapping. This parameter change transforms the storage mechanism from one that causes cumulative dielectric damage to one that relies on trapped charges in the oxide layer, thereby improving endurance without requiring dielectric breakdown
2Productivity
If conventional planar transistors are used, then manufacturing is simpler, but device performance and density are limited
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional tri-gate structures. The gate wraps around the channel in three dimensions, providing superior electrostatic control and enabling higher device density while maintaining manufacturability through established semiconductor processing techniques
Solution Approach 2:
The patent employs composite material structures including metal oxide semiconductor channels combined with high-k dielectric layers and metal gate electrodes. This composite approach enables optimized electrical performance and nonvolatile storage while maintaining compatibility with standard manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a nonvolatile memory device with improved endurance and reliability by eliminating charge tunneling, allowing for longer charge retention times and reduced performance degradation.
Implementation Method 1
stores electrical charges without charge tunneling
Data Source
AI summary
A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.