Tri-Gate Frame Pixel Structure for LCD Storage Capacitor
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Solution Overview
Problem
Conventional IPS liquid crystal display panels suffer from a small storage capacitor capacity and parasitic feed-through effects, leading to poor display quality and increased cross-talk due to the limited capacity of the storage capacitor and the one-to-one correspondence of data lines and scan lines.
Innovation Solution
A tri-gate frame pixel structure is introduced, where a storage capacitor with a first and second via connects the capacitor layers, increasing its capacity and reducing parasitic capacitance, and a thin film transistor is formed simultaneously, enhancing the display quality by reducing feed-through effects and cross-talk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the traditional one-to-one correspondence of data lines and scan lines is used, then the pixel structure is simple, but the storage capacitor capacity is too small causing feed through effect and poor display quality
Solution Approach 1:
The patent merges the storage capacitor formation into the same manufacturing process as the thin film transistor, using shared process steps (sputtering capacitor layers, forming vias) to simultaneously create both components. This integration increases storage capacitor capacity to reduce feed through effect while avoiding the need for separate additional processing stages, thus improving display quality without proportionally increasing device complexity
Solution Approach 2:
The patent extends the storage capacitor into the lower portion of the common line, utilizing the vertical dimension and available space beneath the common line structure. This dimensional extension significantly increases the storage capacitor capacity without occupying additional lateral pixel area, thereby improving display quality while maintaining compact pixel structure
2Reliability
If the storage capacitor capacity is increased by extending into the common line, then the feed through effect is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent combines the storage capacitor manufacturing steps with the thin film transistor fabrication process. The same sputtering equipment and process parameters are used to form capacitor layers alongside transistor layers, and the same via formation processes are used for both component interconnections. This merging approach increases storage capacitor capacity to reduce feed through effect while maintaining manufacturing process simplicity through process integration
Solution Approach 2:
The patent designs the capacitor layers and via structures to serve dual functions: forming the storage capacitor in the upper portion and providing interconnections for the thin film transistor. The lower portion of the common line serves both as an electrical conductor and as an extended storage capacitor region. This multi-functionality reduces the need for separate manufacturing steps, thereby improving ease of manufacture while achieving feed through effect reduction
3Object-generated harmful factors
If the parasitic capacitor between data line and pixel electrode is reduced, then the cross talk phenomenon is improved, but the storage capacitor design becomes more complex
Solution Approach 1:
The patent extracts the storage capacitor function from the traditional capacitor location and extends it into the lower portion of the common line. This separation of the storage capacitor from the immediate data line-pixel electrode interface reduces parasitic capacitance between the data line and pixel electrode, thereby improving cross talk performance. The storage capacitor design complexity is managed through integration with existing common line structures
Solution Approach 2:
The patent introduces the extended lower portion of the common line as an intermediary structure that serves as both the storage capacitor and a shielding element. This intermediary structure physically separates the data line from the pixel electrode, reducing parasitic capacitance and cross talk, while the storage capacitor design remains relatively simple by utilizing this intermediary structure
Data Source
AI summary
A pixel structure of a liquid crystal display panel and a manufacturing method thereof are provided, the pixel structure adopts a tri-gate frame, and one thin film transistor and one storage capacitor are simultaneously formed during the manufacturing process. The storage capacitor has a first via and a second via to connect a first capacitor layer and a second capacitor layer of the storage capacitor. A main storage portion of the storage capacitor further includes a lower portion of a common line, so as to substantially increase the capacity of the storage capacitor and reduce a feed through effect produced by the parasitic capacitor of the liquid crystal display panel, and to improve the display quality of the panel.