Tri-Gate Thin-Film Transistor Structure to Minimize Channel Resistance
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Solution Overview
Problem
Current thin film transistors (TFTs) face challenges in achieving high on/off current ratios and minimizing high resistance regions within channels, which are essential for efficient memory switch applications.
Innovation Solution
A tri-gate TFT configuration is introduced, featuring three gate electrodes that control current flow through two top and two bottom channels, with a center gate electrode and off-center gate electrodes formed on opposite sides of an active region, providing an areal overlap to eliminate or minimize high resistance regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TFT structures are used, then device complexity is low, but on/off current ratio is insufficient
Solution Approach 1:
The gate electrode is segmented into multiple distinct gate electrodes (first gate electrode, second gate electrode, third gate electrode) positioned at different locations. This segmentation allows independent control of different channel regions, enabling higher on/off current ratio by selectively controlling current flow through various paths while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent transitions from a planar gate configuration to a three-dimensional arrangement with gate electrodes positioned at different heights and locations (top gate, bottom gate, and side gate). This dimensional expansion creates multiple control dimensions for current flow, achieving superior on/off current ratio while the systematic arrangement keeps device complexity controllable.
2Reliability
If conventional TFT structures are used, then manufacturing process is simple, but high resistance regions cannot be minimized
Solution Approach 1:
Different gate electrodes are positioned to provide localized control over specific channel regions. The first gate electrode controls one region, the second gate electrode controls another region, and the third gate electrode controls a third region. This localized control allows minimization of high resistance regions in specific areas without requiring complete redesign of the entire fabrication process, balancing improved channel resistance with manufacturing feasibility.
Solution Approach 2:
The multiple gate electrodes act as intermediaries between the control terminals and the channel regions, providing distributed control to minimize resistance. Rather than using a single complex control mechanism, the patent employs multiple simpler gate electrodes that collectively achieve superior resistance control through their combined effect on different channel segments.
3Productivity
If tri-gate configuration is implemented, then current control is improved, but device complexity increases
Solution Approach 1:
The multiple gate electrodes are designed to serve multiple functions: they collectively control current flow through the channel, provide independent control of different channel regions, and enable adjustment of threshold voltage. This multi-functionality achieves superior current control efficiency while avoiding the need for additional separate components, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the control functions of multiple gate electrodes into a unified tri-gate configuration where the first, second, and third gate electrodes work together to control current flow. This consolidation of control functions into a single integrated structure achieves improved current control efficiency while keeping device complexity manageable through the unified design approach.
Data Source
AI summary
A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.