Tri-Gate Thin-Film Transistor Layout for High On/Off Current Ratio
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Solution Overview
Problem
Current thin film transistors (TFTs) face challenges in achieving high on/off current ratios and minimizing high resistance regions within channels, which are essential for efficient memory switch applications.
Innovation Solution
A tri-gate TFT configuration with three gate electrodes, including a center gate electrode and two off-center gate electrodes, is implemented to control current flow through four channels, providing a high on/off current ratio by eliminating or minimizing high resistance regions through areal overlap between the center and off-center gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TFT structures are used, then device complexity is low, but on/off current ratio is insufficient
Solution Approach 1:
The gate electrode is segmented into three separate gate electrodes (first gate electrode, second gate electrode, and third gate electrode) positioned at different locations around the semiconductor channel. This segmentation allows independent control of different channel regions, enabling high on/off current ratio by selectively controlling current flow through each channel segment while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent transitions from a conventional planar single-gate structure to a three-dimensional multi-gate configuration where gate electrodes are positioned at different spatial locations (top, bottom, and side gates) around the channel. This dimensional change provides superior electrostatic control and eliminates high resistance regions by controlling current flow from multiple directions, achieving high on/off current ratio without proportionally increasing device complexity.
2Reliability
If single gate electrode is used, then manufacturing process is simple, but high resistance regions exist within channels
Solution Approach 1:
Different gate electrodes are positioned to control specific local regions of the semiconductor channel. The first gate electrode controls a first channel region, the second gate electrode controls a second channel region, and the third gate electrode controls a third channel region. This local quality approach ensures uniform resistance control throughout the channel by addressing each region's specific electrical characteristics, while the standardized formation process for each gate electrode maintains manufacturing simplicity.
Solution Approach 2:
The patent introduces gate electrodes from multiple spatial dimensions (top gate, bottom gate, and side gate) to control different portions of the channel. This multi-dimensional approach eliminates high resistance regions by providing comprehensive electrostatic control throughout the channel volume, while each gate electrode can be formed using standard deposition and patterning techniques that maintain ease of manufacture.
3Reliability
If multi-gate configuration is implemented, then channel current control is improved, but device fabrication complexity increases
Solution Approach 1:
The channel is segmented into multiple regions controlled by separate gate electrodes, allowing independent optimization of current flow through each segment. This segmentation improves channel current control by enabling selective activation and threshold voltage adjustment for each gate-channel combination, while the modular nature of the segmented architecture allows systematic fabrication using repeated process modules rather than entirely new complex processes.
Solution Approach 2:
Each gate electrode structure serves multiple functions: controlling threshold voltage, modulating channel current, and eliminating high resistance regions. The first, second, and third gate electrodes work together as an integrated multi-functional system that provides comprehensive channel control. This multi-functionality is achieved through coordinated design of the gate electrodes and their respective control circuits, allowing improved channel current control without proportionally increasing fabrication complexity through shared process steps.
Data Source
AI summary
A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.


