Tri-Layer Bottom Dielectric Isolation for Nanosheet FET Leakage Control
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Solution Overview
Problem
Current semiconductor fabrication processes for nanosheet FETs face challenges in maintaining the effectiveness of the bottom dielectric isolation (BDI) layer, which is prone to erosion during subsequent processing steps, leading to increased source/drain leakage and degraded device performance.
Innovation Solution
A tri-layer bottom dielectric isolation (BDI) structure is introduced, comprising a high-k dielectric layer sandwiched between a spacer material and another high-k dielectric layer, providing enhanced etch resistance and electrical isolation for the source/drain regions from the semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer bottom dielectric isolation is used, then the device structure is simple, but the BDI layer is prone to erosion during processing
Solution Approach 1:
The single-layer BDI is segmented into a multi-layer structure consisting of a first high-k dielectric layer, a spacer material layer, and a second high-k dielectric layer. This segmentation provides gradient etch resistance, where each layer serves a specific function: the first high-k layer provides initial isolation, the spacer material provides etch resistance during critical processing steps, and the second high-k layer provides additional isolation and protection.
Solution Approach 2:
The BDI structure uses composite materials combining different dielectric materials with complementary properties. The high-k dielectric materials provide excellent electrical isolation properties, while the spacer material provides superior etch resistance. This composite approach allows the BDI to simultaneously achieve both electrical isolation effectiveness and resistance to processing-induced erosion.
2Productivity
If process steps are performed after BDI formation, then device fabrication can proceed, but the BDI layer erodes reducing isolation effectiveness
Solution Approach 1:
The multi-layer BDI structure is formed preliminarily before subsequent processing steps to provide a robust foundation that can withstand upcoming fabrication processes. The spacer material layer is specifically positioned to provide etch resistance during critical subsequent steps such as source/drain region formation and gate stack processing, preventing thickness reduction before these steps occur.
Solution Approach 2:
The spacer material layer acts as a protective cushion between the high-k dielectric layers, absorbing and resisting etch attacks during subsequent processing. This beforehand cushioning prevents the high-k dielectric layers from being directly exposed to erosive processing conditions, maintaining BDI thickness and effectiveness throughout the fabrication sequence.
3Ease of manufacture
If conventional BDI is used, then source/drain regions can be formed, but parasitic leakage increases due to BDI erosion
Solution Approach 1:
The spacer material, which has superior etch resistance, is strategically positioned to convert the harmful effect of processing-induced erosion into a beneficial protective barrier. During source/drain region formation and other subsequent steps, the spacer material absorbs the erosive effects that would otherwise damage the BDI and increase leakage, thereby protecting the electrical isolation and preventing parasitic source-to-drain leakage paths.
Data Source
AI summary
A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.