Tri-Layer Etch Stop Structure for Low-Capacitance Source/Drain Contacts

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Solution Overview

Problem

The challenge in semiconductor manufacturing is the undesired oxidation of source/drain structures during the formation of etch stop layers, which affects the dielectric constant and increases parasitic capacitance, thereby degrading device performance.

Innovation Solution

A tri-layer etch stop layer comprising a nitrogen-free low-k dielectric layer, an oxygen-treated low-k dielectric layer, and a dielectric layer is formed using low-temperature, short-duration deposition processes to minimize oxidation and reduce parasitic capacitance between source/drain contacts and gate stacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional etch stop layers are formed using standard deposition processes, then the etch stop layer provides adequate protection and etching selectivity, but oxidation of source/drain structures occurs and parasitic capacitance increases

Engineering Contradiction:
Improveprotection of source/drain structuresVSAvoidoxidation of source/drain structures
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the deposition parameters by using low-temperature processing (below 400°C) and controlling oxygen exposure during deposition. This prevents oxidation of the source/drain structures while still forming an effective etch stop layer with appropriate dielectric constant

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates a multi-layer etch stop structure where different layers have different compositions and properties. The first etch stop layer has reduced oxygen content to minimize oxidation, while the second layer provides additional protection, creating local quality variations to solve the oxidation problem

Inventive Principle:
Principle #3Local quality

2Reliability

If standard dielectric layers are used for etch stop layers, then the layers provide sufficient thickness and coverage, but the dielectric constant is high which increases parasitic capacitance

Engineering Contradiction:
Improveetch stop layer coverageVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the dielectric material composition by using silicon oxycarbide instead of conventional silicon oxide, and by controlling the oxygen content during deposition. This reduces the dielectric constant from typical values of 3.9-4.5 to below 3.5, thereby reducing parasitic capacitance while maintaining adequate coverage

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses composite dielectric materials combining silicon, oxygen, and carbon in specific ratios. The silicon oxycarbide composite provides lower dielectric constant compared to pure silicon oxide, reducing parasitic capacitance while maintaining the etch stop layer's protective function

Inventive Principle:
Principle #40Composite materials

3Manufacturing precision

If high-temperature deposition processes are used to form etch stop layers, then the layers achieve good density and adhesion, but oxidation of source/drain structures is accelerated

Engineering Contradiction:
Improvedensity and adhesion of etch stop layerVSAvoidoxidation rate of source/drain structures
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent changes the temperature parameter by using low-temperature deposition (below 400°C) instead of conventional high-temperature processes. This reduces oxidation rates while achieving adequate density and adhesion through controlled deposition conditions and multi-layer structuring

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The tri-layer etch stop layer effectively prevents oxidation of source/drain structures and reduces parasitic capacitance, enhancing the overall performance of semiconductor devices by improving conductivity and reducing unwanted capacitance.

Implementation Method 1

undesired oxidation of source/drain structures during the formation of etch stop layers

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

reduces parasitic capacitance between source/drain contacts and gate stacks

Methodology Applied
Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20250374601A1Semiconductor Device and Method of Manufacturing the Same
Publication Date: 2025.12.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250374601A1 patent drawing
  • US20250374601A1 patent drawing
  • US20250374601A1 patent drawing

AI summary

A method includes forming a tri-layer etch stop layer over a source/drain, for example, by forming a nitrogen-free low-k dielectric layer on the source/drain, forming an oxygen-treated low-k dielectric layer on the nitrogen-free low-k dielectric layer, and forming a dielectric layer on the oxygen-treated low-k dielectric layer. The nitrogen-free dielectric layer has a first dielectric constant, the oxygen-treated low-k dielectric layer has a second dielectric constant that is greater than the first dielectric constant, and the dielectric layer has a third dielectric constant that is greater than the second dielectric constant and the first dielectric constant. The method may further include forming an interlayer dielectric layer over the tri-layer etch stop layer, removing a portion of the tri-layer etch stop layer and a portion of the ILD layer to form a source/drain contact opening that exposes the source/drain, and forming a source/drain contact structure in the source/drain contact opening.