Tri-Level DAC Switching for Reference Mismatch Suppression
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Solution Overview
Problem
Conventional tri-level digital-to-analog converters (DACs) suffer from non-linear distortion due to static mismatch between reference circuits and total harmonic distortion (THD) degradation, especially when a common-mode feedback (CMFB) circuit is connected to a transimpedance amplifier.
Innovation Solution
A tri-level DAC element with a switch circuit that controls the interconnection between reference circuits and an output port, allowing for mismatch suppression by coupling at least one reference circuit to the output during a '0' state, and optionally using doubled sampling frequency or cell swapping for further noise suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CMFB circuit is connected to a transimpedance amplifier to mitigate non-linear distortion, then non-linear distortion is reduced, but total harmonic distortion degrades due to drain voltage modulation
Solution Approach 1:
The patent applies periodic action by implementing a tri-level DAC element that periodically switches between three distinct states (0, 1, 2) rather than conventional bi-level switching. This periodic tri-level operation allows the circuit to periodically connect reference circuits to the output during the '0' state, creating a rhythmic correction pattern that suppresses mismatch errors while managing drain voltage modulation effects through controlled periodic transitions
2Area of stationary object
If conventional tri-level DAC element is used without CMFB circuit, then area efficiency is maintained, but non-linear distortion occurs due to static mismatch between reference circuits
Solution Approach 1:
The patent implements self-service by enabling the DAC element to automatically suppress its own mismatch errors through the periodic tri-level operation. During the '0' state, the reference circuits are periodically connected to the output, allowing the circuit to self-correct static mismatch between PMOS and NMOS reference circuits without requiring external CMFB circuits, thereby maintaining area efficiency while improving linearity
Data Source
AI summary
A tri-level digital-to-analog converter (DAC) element includes a first DAC cell. The first DAC cell includes a first reference circuit, a second reference circuit, and a switch circuit. The first reference circuit provides a first reference signal. The second reference circuit provides a second reference signal. The first switch circuit receives a control input from an input port of the tri-level DAC element, and controls interconnection between the first reference circuit, the second reference circuit, and an output port of the tri-level DAC element according to the control input. During a period in which the tri-level DAC element operates in a “0” state, the first switch circuit is arranged to couple at least one of the first reference circuit and the second reference circuit to the output port of the tri-level DAC element.