Tri-Level Dynamic Element Matching for Low-Power Multi-Bit DACs
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Solution Overview
Problem
Multi-bit digital-to-analog converters (DACs) face challenges in reducing power consumption, peak reference current, and signal-dependent loading, which lead to distortion and increased power dissipation, especially in low-power systems and switched capacitor implementations.
Innovation Solution
A rotation-based first-order noise-shaping Dynamic Element Matching (DEM) technique is applied using 3-level DAC unit elements, which reduces reference loading and power consumption by employing a mid-point element and adjusting the connection of capacitors to reference voltages, thereby minimizing the peak reference current and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If 2-level DAC elements are used with conventional DEM techniques, then mismatch distortion is reduced, but the number of DAC elements and circuit complexity increase
Solution Approach 1:
The patent changes the state parameter of DAC elements from 2-level to 3-level, allowing elements to assume three distinct voltage states (Vref, Vref/2, 0V) instead of two. This parameter change enables the same noise-shaping DEM functionality to be achieved with fewer elements, directly reducing circuit complexity while maintaining distortion performance
Solution Approach 2:
The invention adds an intermediate voltage level dimension to the DAC elements, creating a tri-level structure with mid-point elements. This dimensional expansion from binary to ternary states allows the system to achieve equivalent or superior linearity performance with reduced element count by utilizing the additional voltage state for more efficient signal representation
2Manufacturing precision
If maximum reference current is drawn to remove signal dependency, then signal distortion is reduced, but power consumption increases
Solution Approach 1:
The patent changes the operational parameter of reference current from maximum constant current to dynamically adjusted current levels. By utilizing 3-level elements, the reference current can be scaled down while maintaining adequate signal drive capability, as the mid-point elements require only Vref/2 current, thereby reducing power consumption while preserving signal integrity
Solution Approach 2:
Instead of always drawing maximum reference current, the system applies partial action by scaling the reference current to the minimum necessary level for each operating condition. The 3-level element structure allows the reference current to be adjusted partially based on the actual signal requirements, avoiding excessive current draw and reducing power consumption while maintaining sufficient signal drive
3Use of energy by moving object
If peak reference current is reduced, then power consumption decreases, but voltage droop and distortion increase
Solution Approach 1:
The patent changes the voltage level parameter of DAC elements to include a mid-point state at Vref/2. This parameter change allows the system to operate with reduced peak reference current while maintaining adequate voltage drive capability, as the intermediate voltage level provides sufficient signal amplitude without requiring maximum current, thereby reducing voltage droop
Solution Approach 2:
By adding the intermediate voltage dimension, the system can achieve adequate signal drive with lower current levels. The tri-level structure provides an additional voltage dimension that compensates for the reduced current, maintaining voltage droop performance while enabling lower power consumption operation
4Device complexity
If 3-level DAC elements are used, then circuit complexity is reduced, but signal-dependent loading characteristics change
Solution Approach 1:
The patent changes the state parameter of DAC elements to 3-level, which fundamentally alters the signal-dependent loading characteristics. The mid-point elements drawing Vref/2 current create a different loading profile compared to conventional 2-level elements, requiring adjusted reference buffer design to maintain constant loading and minimize distortion
Data Source
AI summary
Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.