Tri-Level Forced Transition Encoding for ISI and DC Creep

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Solution Overview

Problem

Existing data encoding techniques fail to effectively mitigate intersymbol interference (ISI) and DC creep in high-speed data transmissions, particularly in bandwidth-limited channels, often exacerbating sensing errors and increasing system complexity.

Innovation Solution

A 2-bit tri-level forced transition encoding scheme that maps two consecutive NRZ data bits into two new encoded bits, ensuring transitions between three possible logic states (-1, 0, and +1), preventing any logic state from predominating and causing DC creep, while maintaining the same duration as the original bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional encoding methods (NRZ, RZ, Bi-NRZ, Manchester, 4-PAM) are used, then data transmission is achieved, but DC creep and intersymbol interference occur due to pulse dispersion in bandwidth-limited channels

Engineering Contradiction:
Improvesignal integrityVSAvoidDC creep and intersymbol interference
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the voltage level parameters from traditional binary levels to tri-level encoding with forced transitions, using voltage levels of -Vcc, 0V, and +Vcc. This parameter change ensures that no more than two consecutive encoded bits have the same logic state, preventing DC creep while maintaining signal integrity in bandwidth-limited channels.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The encoding scheme implements periodic transitions by forcing the encoded signal to transition between different logic states at regular intervals. Specifically, the encoding ensures that transitions occur systematically to prevent any logic state from predominating for extended periods, thereby eliminating DC creep through periodic state changes.

Inventive Principle:
Principle #19Periodic action

2Stability of the object's composition

If encoding schemes that prevent DC creep are implemented, then signal stability improves, but sensing complexity increases due to multiple voltage levels

Engineering Contradiction:
ImproveDC bias stabilityVSAvoidsensing complexity
Core Design Contradiction:
Stability of the object's compositionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent uses tri-level voltage parameters (-Vcc, 0V, +Vcc) with forced transitions that create a systematic pattern. This parameter selection allows for stable DC bias while enabling sensing with only two threshold voltages, as the forced transition property reduces the number of distinct sensing levels needed compared to traditional multi-level encoding schemes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The encoding scheme uses three voltage levels but with forced transitions that effectively reduce the sensing requirement to two thresholds. This partial use of the available voltage levels optimizes the sensing complexity by not requiring full utilization of all possible level combinations, thereby simplifying the detection process while maintaining stability.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If higher data rates are transmitted, then productivity increases, but intersymbol interference worsens due to pulse dispersion in bandwidth-limited channels

Engineering Contradiction:
Improvedata transmission rateVSAvoidintersymbol interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the encoding parameters to tri-level with forced transitions, which reduces the effective frequency content and pulse dispersion. By ensuring systematic transitions between logic states, the encoding scheme reduces intersymbol interference effects, enabling higher data rates to be transmitted through bandwidth-limited channels without excessive pulse dispersion.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7492287B2Two-bit tri-level forced transition encoding
Publication Date: 2009.02.17 MICRON TECHNOLOGY INC
  • US7492287B2 patent drawing
  • US7492287B2 patent drawing
  • US7492287B2 patent drawing

AI summary

An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between ‘−1’ and ‘0’ logic states, or ‘+1’ and ‘0’ logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep.