Tri-Level Pin Input Circuit for Low-Leakage Signal Detection
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Solution Overview
Problem
Traditional tri-level pins and their associated circuitry face issues such as leakage current, misinterpretation of signals, and exposure to electrostatic discharges, leading to high quiescent currents and unnecessary power consumption.
Innovation Solution
The proposed input voltage detection circuit includes a pin, an input buffer, a voltage divider circuit, and current mirror circuits that drive the pin to a predetermined level when floating, mitigating leakage current and avoiding direct coupling to transistor gate terminals, thereby reducing power consumption and protecting against electrostatic discharges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional tri-level pins are used to detect high, low, or floating states, then signal detection capability is improved, but leakage current increases and power consumption rises
Solution Approach 1:
The patent introduces an intermediary circuit between the pin and the detection logic that includes transmission gates and level shifters. This intermediary structure controls the coupling between the pin and internal nodes, enabling precise detection of high, low, or floating states while minimizing direct leakage paths to ground or VDD, thus reducing quiescent current.
Solution Approach 2:
The patent dynamically changes the electrical parameters (impedance, coupling strength) of the detection circuit based on the detected state. When a pin is detected as floating, the circuit adjusts its parameters to maintain detection sensitivity while reducing power consumption by disconnecting or high-impedance coupling certain internal nodes, thereby resolving the contradiction between detection precision and power loss.
2Speed
If pins are directly coupled to transistor gate terminals for signal detection, then detection speed is improved, but exposure to electrostatic discharges increases
Solution Approach 1:
The patent places transmission gates and level shifters as intermediary elements between the pin and the transistor gate terminals. These intermediaries provide galvanic isolation and voltage level translation, protecting the internal transistor gates from electrostatic discharge while maintaining fast detection response through controlled signal coupling.
Solution Approach 2:
The circuit design incorporates protective structures that are activated before electrostatic discharge can reach vulnerable nodes. The transmission gates can be pre-configured to block discharge paths, and the level shifters provide voltage clamping that cushions against voltage spikes, thereby protecting the transistor gates from ESD damage while preserving detection functionality.
3Device complexity
If floating pins are not actively driven to a predetermined level, then circuit simplicity is maintained, but leakage current increases and signal misinterpretation occurs
Solution Approach 1:
The patent implements preliminary action by actively driving floating pins to a predetermined voltage level (such as VDD or ground) through controlled activation of transmission gates and pull-up/pull-down networks. This preliminary driving occurs before the detection logic evaluates the pin state, ensuring that floating conditions are resolved and preventing misinterpretation of indeterminate voltage levels as valid logic states.
Data Source
AI summary
In examples, an apparatus comprises a pin, an input buffer coupled to the pin at an output of the input buffer, a voltage divider circuit coupled to the input buffer at an input of the input buffer, a first current mirror coupled to the input buffer, and a second current mirror coupled to the input buffer. The apparatus also comprises a first output buffer coupled between the input buffer and the first current mirror, and a second output buffer coupled between the input buffer and the second current mirror.