Tri-Level PWM Amplifier for Filterless Audio Efficiency
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Solution Overview
Problem
Conventional audio amplifiers face challenges in balancing fidelity and power efficiency, particularly in handheld devices where battery life and cooling capacity are limited, with Class AB amplifiers being inefficient and Class D amplifiers requiring high switching frequencies to maintain fidelity.
Innovation Solution
A filterless, DC-free amplifier design that generates tri-level output signals using pulse-width modulated (PWM) signals, integrating feedback and comparator signals to control transistors for efficient voltage delivery, reducing power consumption while maintaining audio fidelity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Class AB amplifier is used, then audio fidelity is maintained, but power efficiency deteriorates
Solution Approach 1:
The patent changes the operating parameters of the amplifier by using pulse-width modulation (PWM) technique where the duty cycle of the PWM signal is varied to control the output voltage. This allows the amplifier to operate in a switching mode rather than linear mode, significantly improving power efficiency while maintaining audio fidelity through precise duty cycle control that accurately reproduces the input audio signal.
Solution Approach 2:
The patent employs periodic PWM signals to drive the amplifier stages. The PWM controller generates periodic pulse trains with varying duty cycles that correspond to the audio input signal. This periodic switching action replaces continuous linear amplification, reducing power consumption while maintaining signal fidelity through the periodic nature of the modulation that preserves the audio waveform characteristics.
2Measurement precision
If Class D amplifier with high switching frequency is used, then audio fidelity is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the PWM duty cycle that adapts to the instantaneous amplitude of the audio signal. The amplifier dynamically adjusts switching parameters and operates in different modes (Class A, AB, or B) depending on signal conditions, optimizing the balance between fidelity and power consumption in real-time rather than using fixed high-frequency switching throughout.
Solution Approach 2:
The patent changes the switching frequency dynamically rather than operating at fixed high frequency. The PWM controller adjusts switching frequency based on signal characteristics and load conditions, lowering frequency during low-power periods to reduce switching losses while maintaining sufficient frequency during high-fidelity requirements, thus resolving the contradiction between fidelity and power consumption.
3Measurement precision
If filtering components are added to Class D amplifier, then output signal quality is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the traditional LC low-pass filter components from the Class D amplifier architecture. Instead of using separate filtering stages, the invention integrates filtering functionality directly into the feedback loop and PWM control mechanism, where the feedback capacitor and control circuitry perform the filtering function, thereby eliminating bulky inductors and capacitors while maintaining output signal quality.
Solution Approach 2:
The patent merges the filtering function with the feedback and control circuitry. The feedback capacitor in the integrator stage and the PWM controller work together to perform both amplification and filtering functions simultaneously. This consolidation eliminates the need for separate filtering components, reducing device complexity while preserving output signal quality through the integrated control mechanism.
Data Source
AI summary
An amplifier generates a tri-level output signal in response to an input signal that is pulse-width modulated. The amplifier is filterless and DC free. The amplifier includes an integrator, a signal generator, comparator, a switch pulse logic block, a driver, and a control block. The control block supplies a multitude of pulse-width modulated (PWM) signals in response to the received digital input signal. A pair of the PWM signals are applied to the signal generator which in response supplies a signal to the integrator. The integrator's output signal is compared to a reference signal by the comparator. The switch pulse logic block receives the output of the comparator and a pair of delayed PWM signals and in response generates a multitude of driver signals applied to the driver. The driver supplies an output signal that is adapted to vary between first, second and third voltages.