Tri-Loop CDR Clock Cleaning for Independent Jitter Control
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Solution Overview
Problem
Current clock and data recovery (CDR) circuits face limitations in independently adjusting jitter tolerance and jitter transfer levels, leading to restricted clock cleaning capabilities and increased costs due to the need for multiple oscillators to support various frequencies, which results in performance degradation and increased board space.
Innovation Solution
A tri-loop architecture that includes a CDR loop for data recovery, a clock generation loop with a fractional N-divider for independent jitter transfer settings, and a control loop to manage jitter tolerance, allowing for reconfigurability and reduced jitter generation using a single low-cost oscillator that can operate at arbitrary frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single CDR circuit uses a single oscillator to support multiple frequencies, then board space and cost are reduced, but the oscillator frequency must be an integer division of the desired data rate which limits frequency flexibility
Solution Approach 1:
The patent changes the fundamental parameter of frequency relationship from integer division to arbitrary frequency division. The oscillator frequency no longer needs to be an integer multiple or divisor of the data rate, allowing continuous frequency adjustment while using a single oscillator across multiple applications.
2Adaptability or versatility
If multiple oscillators are used to support different frequencies in a single CDR circuit, then frequency flexibility is improved, but board space and cost increase
Solution Approach 1:
The patent makes a single oscillator serve multiple frequency requirements through arbitrary frequency division. The same oscillator can support different data rates and clock frequencies by adjusting the division ratio, eliminating the need for multiple dedicated oscillators for different frequency bands.
Solution Approach 2:
The system dynamically adjusts the oscillator frequency and division ratio to match different operating conditions. The oscillator frequency is no longer fixed but can be tuned to arbitrary values, and the division ratio is dynamically changed to achieve the desired output frequency for different communication standards.
3Reliability
If CDR loop bandwidth is increased to improve jitter tolerance, then jitter tolerance is improved, but jitter transfer also increases which degrades performance
Solution Approach 1:
The patent segments the single CDR loop into two independent loops: an inner CDR loop for data recovery and jitter tolerance, and an outer clock cleaning loop for jitter filtering. This segmentation allows each loop to be optimized independently - the inner loop can have high bandwidth for jitter tolerance while the outer loop provides aggressive jitter filtering.
Solution Approach 2:
The patent introduces an intermediate clock cleaning stage between the CDR output and the final output. This intermediate stage acts as a mediator that cleans the clock signal by filtering jitter before it reaches the final output, allowing the CDR loop to operate with high bandwidth for jitter tolerance while the intermediary provides jitter transfer reduction.
4Object-generated harmful factors
If an external clock cleaning module is used to reduce jitter generation, then jitter performance is improved, but board space and expense increase
Solution Approach 1:
The patent merges the clock cleaning function with the CDR circuit by integrating the clock cleaning loop within the same chip. The clock cleaning loop shares resources with the CDR loop and integrates the phase detector, loop filter, and frequency divider functions into a unified structure, eliminating the need for external clock cleaning modules.
Solution Approach 2:
The patent implements a nested loop structure where the clock cleaning loop encompasses the CDR loop. The inner CDR loop recovers data and clock, while the outer clock cleaning loop cleans the recovered clock signal. This nested architecture allows jitter filtering to be performed internally without requiring separate external components.
Data Source
AI summary
Embodiments of the present invention may provide for independent setting of jitter tolerance and jitter transfer levels, and reduced jitter generation of a data transmission device, such as a clock and data recovery (CDR) circuit or the like. An architecture may provide for reconfigurability of a circuit for use in various applications. The architecture may include a multi-loop structure, such as a tri-loop structure.