Tri-port Memory System for Processor Throughput
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Solution Overview
Problem
Current processor memory access systems are inefficient due to delays caused by direct memory access (DMA) engines 'stealing' memory cycles from processors, leading to processor stalls when accessing both program data and I/O data simultaneously.
Innovation Solution
A high-speed tri-port memory system with separate partitions and ports allows concurrent access to instruction code, program variables, and peripheral data, utilizing a DMA engine to manage I/O data without inhibiting processor access, and employing arbitration for concurrent write access to prevent conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-port memory system is used with DMA engine, then the processor can access memory, but the processor must wait for DMA to complete access causing cycle stealing and processor stalls
Solution Approach 1:
The memory system is segmented into multiple independent ports (first port for peripheral bus, second port for processor instruction/code access, third port for processor data access). Each port can operate simultaneously without interfering with others, allowing the processor to access memory while DMA operates on a different port, thereby eliminating cycle stealing and processor stalls.
2Speed
If separate data and instruction ports are used (Harvard Architecture), then the processor can read instructions and program variables concurrently, but the processor still must wait to access I/O data from peripheral devices
Solution Approach 1:
The third port is designed with universal read/write access to both the first partition (storing peripheral data) and the second partition (storing executable code and program variables). This allows the processor to access I/O data, instructions, and program variables through a single unified interface, improving I/O data access efficiency while maintaining the benefits of separate instruction and data access through the second port.
3Productivity
If the DMA engine has exclusive access to memory partitions, then I/O data can be transferred efficiently, but the processor must wait causing delays
Solution Approach 1:
The system adds a temporal dimension to memory access by introducing multiple ports that operate in parallel across different time cycles. The first port handles DMA transfers to the first partition, while the second and third ports simultaneously handle processor access to the second partition and both partitions respectively. This dimensional expansion allows concurrent operations without resource conflicts, improving both I/O transfer efficiency and processor access timing.
Data Source
AI summary
Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.