Tri-State Buffering for Pseudo Dual-Port Memory Access
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Solution Overview
Problem
Conventional pseudo dual-port memory designs experience access time degradation due to the use of extra multiplexers, which is not present in single-port memory speeds, necessitating an improvement to overcome this delay.
Innovation Solution
The implementation of a pseudo dual-port memory design that avoids the use of extra multiplexers by utilizing the SD and NSD output nodes of the sense amplifier for both single-port and dual-port operations, allowing the same memory cells to be used for both configurations, including programmable functionality, thereby reducing access time delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If extra multiplexers are added to support dual-port operations in conventional pseudo dual-port memory designs, then dual-port functionality is achieved, but access time degrades compared to single-port memory speeds
Solution Approach 1:
The patent removes the extra multiplexers from the conventional pseudo dual-port memory design. Instead of using multiplexers to switch between single-port and dual-port modes, the invention directly connects the sense amplifier outputs to separate output buffers for each port, eliminating the multiplexer delay and achieving single-port speed performance while maintaining dual-port functionality.
Solution Approach 2:
The sense amplifier outputs are designed to serve multiple functions simultaneously - the same sense amplifier can serve both PORTA and PORTB operations without requiring multiplexer switching. This multi-functionality approach allows the memory to operate in both single-port and dual-port modes without the performance penalty of extra multiplexing logic.
2Adaptability or versatility
If multiplexers are added at the output to support outputs of both PORTA and PORTB, then dual-port output support is achieved, but timing associated with multiplexer control degrades access time even for PORTA
Solution Approach 1:
The patent segments the output path by providing separate output buffers for PORTA and PORTB that connect directly to the sense amplifier outputs. This segmentation eliminates the need for a single multiplexer controlling both ports, allowing each port to have its own dedicated output path and achieve single-port speed performance.
3Adaptability or versatility
If conventional 6T bitcell designs are used with bolt-on circuitry for dual-port operations, then dual-port functionality is added, but access time performance degrades compared to single-port memory
Solution Approach 1:
The patent merges the dual-port functionality directly into the sense amplifier and output buffer architecture rather than adding it as separate bolt-on circuitry. By integrating the dual-port capability at the sense amplifier level with direct connections to output buffers, the design achieves dual-port operations without the performance degradation associated with additional external logic.
Data Source
AI summary
Various implementations described herein are related to a device having a sense amplifier with multiple output ports. The device may include tri-state buffer circuitry having multiple tri-state buffers coupled to the multiple output ports of the sense amplifier. The device may include latch circuitry having multiple latches coupled to the multiple tri-state buffers of the tri-state buffer circuitry.