Tri-state buffer test pad for stacked semiconductor bump reliability
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Solution Overview
Problem
In stacked semiconductor devices, direct contact with bump electrodes for testing can cause connection failures due to needle marks, and using test pads increases the load capacity of bump electrodes, which is undesirable for high-speed operations.
Innovation Solution
Incorporating a tri-state buffer coupled between the penetrating electrode and the test pad, controlled by a buffer control signal, allows for testing without direct probing of bump electrodes, minimizing load capacity and preventing connection failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a tester probe is directly applied to the bump electrode for testing, then testing can be performed, but needle marks are left on the bump electrode causing connection failure
Solution Approach 1:
The patent introduces a test pad as an intermediary element between the tester probe and the bump electrode. The test pad is formed on the semiconductor chip surface and electrically connected to the bump electrode through a penetrating electrode. During testing, the probe contacts the test pad instead of directly contacting the bump electrode, thus avoiding needle marks while maintaining electrical connection for testing purposes.
2Reliability
If a test pad is used to test stacked memory chips, then direct contact with bump electrodes is avoided, but the pad capacity is superimposed on the pin capacity of the bump electrode
Solution Approach 1:
The patent segments the electrical connection path into distinct functional sections: the bump electrode for high-speed signal transmission, the penetrating electrode for vertical connection through the chip, and the test pad for testing operations. By separating the test function from the signal transmission function, the bump electrode maintains its optimized characteristics for high-speed operation while the test pad provides a dedicated interface for testing without affecting the signal path.
3Adaptability or versatility
If the stacked memory chip part and memory controller are prepared separately by different manufacturers, then manufacturing flexibility is improved, but assembly complexity increases
Solution Approach 1:
The patent employs a standardized bump electrode interface that serves multiple functions: it acts as a test point during chip testing through the test pad connection, and simultaneously serves as the interconnection interface when stacking the memory chip with the memory controller. This universal interface design allows the same structural elements to fulfill both testing and interconnection requirements, simplifying the overall assembly process despite multi-manufacturer production.
Data Source
AI summary
A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.