Tri-State Delay PLL Switching for Fast Lock and Low Jitter
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Solution Overview
Problem
Conventional digital phase lock loops are vulnerable to external influences, leading to phase skew and jitter issues, and struggle to maintain a wide operable frequency range while minimizing phase skew and jitter within a limited die size.
Innovation Solution
A tri-state delay-typed phase lock loop that automatically adjusts the phase and frequency of an input reference signal, using a phase and frequency detector, mode detector, mode selector, counters, and phase and frequency calculator to generate an output synchronous signal identical to the input signal in frequency and phase, with mechanisms to manage edge tracking and recording counter values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital control method is used in phase lock loop, then locking speed is improved and process voltage tolerance is enhanced, but phase skew and jitter increase
Solution Approach 1:
The patent implements dynamic switching between digital and analog delay control modes. The control unit selectively switches the delay control unit between digital control mode (for fast locking) and analog control mode (for low phase skew and jitter during steady state), allowing the system to optimize performance at different operational stages
Solution Approach 2:
The patent employs periodic mode switching where the phase lock loop initially operates in digital control mode for rapid acquisition, then transitions to analog control mode for precise steady-state operation. This periodic action between different control modes resolves the contradiction between fast locking and low phase skew
2Manufacturing precision
If delay time of delay unit is reduced to minimize phase skew and jitter, then phase precision is improved, but operable frequency range decreases
Solution Approach 1:
The patent implements dynamic adjustment of delay unit parameters through the control unit. The system can adaptively modify the delay time based on operating conditions, allowing minimal delay for high precision when needed and larger delay for extended frequency range coverage, thus resolving the contradiction between phase precision and frequency range adaptability
Solution Approach 2:
The patent changes the delay time parameter dynamically based on operational requirements. By adjusting this critical parameter, the system can optimize for either phase precision or frequency range depending on the current operating state, resolving the fixed trade-off between these two parameters
3Adaptability or versatility
If wider operable frequency range is achieved, then adaptability is improved, but locking duration increases
Solution Approach 1:
The patent employs dynamic mode switching where the system operates in digital control mode during the locking acquisition phase (regardless of frequency range) to minimize locking duration, then transitions to analog control mode for steady-state operation. This dynamic approach maintains wide frequency range adaptability while preventing excessive locking duration
4Ease of operation
If conventional phase frequency detector is used to detect edge triggering, then state change control is achieved, but vulnerability to external influences increases causing phase detector malfunction
Solution Approach 1:
The patent implements feedback mechanisms where the control unit continuously monitors the operation state and selectively controls the delay control unit based on detected conditions. This feedback loop prevents external influences from causing phase detector malfunction by adaptively adjusting the control strategy
Solution Approach 2:
The patent introduces a control unit as an intermediary between the phase frequency detector and the delay control unit. This intermediary selectively controls the delay based on operation state, protecting the phase detector from external influences while maintaining proper state change control
Data Source
AI summary
The present invention relates to a tri-state delay-typed phase lock loop, which comprises: a phase and frequency detector, a mode detector, a mode selector, a first sampling delay unit, a plurality of counters, a second sampling delay unit, and a phase and frequency calculator. The phase and frequency of the input reference signal can be determined automatically by the phase lock loop, and the output synchronization signal can be generated such that the frequency and the phase of the output synchronization signal are identical to those of the input reference signal.