Tri-State Driver Circuit With Automatic High-Impedance Control
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Solution Overview
Problem
Conventional tri-state driver circuits require additional circuitry and power to manage a separate enable signal, especially at high clock speeds, leading to increased substrate area and power consumption due to the need for precise timing coordination.
Innovation Solution
A signal driver circuit that provides automatic tri-state control using a true input signal and its complement, eliminating the need for a separate enable signal by utilizing a delay line, boost circuit, and enable circuit to manage logic levels and impedance states without additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate enable signal is used to control the high-impedance state of the driver circuit, then the driver circuit can be placed into a tri-state condition, but additional circuitry is required that consumes substrate area and electrical power
Solution Approach 1:
The patent combines the enable signal generation function with the existing input signal processing circuitry. The delay line and logic circuits that process the input signal also generate the enable signal, eliminating the need for a completely separate enable signal path and reducing overall circuit complexity while maintaining tri-state capability
Solution Approach 2:
The input signal processing circuitry is designed to perform multiple functions: it processes the input signal for logic level determination and simultaneously generates the enable signal for tri-state control. This multi-functionality reduces the need for dedicated separate circuitry
2Adaptability or versatility
If a separate enable signal is used to control the high-impedance state, then the driver circuit can be tri-stated, but precise timing coordination is required which consumes additional power and area
Solution Approach 1:
The delay line is configured to generate the enable signal in advance of when it is needed, based on the timing characteristics of the input signal. This preliminary generation of the enable signal eliminates the need for complex real-time timing coordination circuitry and reduces power consumption by using simple delay elements rather than complex timing control logic
3Measurement precision
If additional circuitry is added to manage the enable signal at high clock speeds, then precise timing control is achieved, but substrate area is increased
Solution Approach 1:
The circuit uses its own input signal and existing logic circuits to generate the enable signal with the required timing precision. The delay line is configured based on the inherent timing characteristics of the input signal, allowing the circuit to self-adjust timing without requiring external timing control circuitry, thereby reducing substrate area
Data Source
AI summary
Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.