Tri-State Driver Circuitry for Memory Power Reduction
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Solution Overview
Problem
As memory storage increases in semiconductor devices like DDR5 SDRAM, the number of data read/write lines and capacitance between them increase, leading to higher power consumption during read and write operations.
Innovation Solution
Implementing tri-state driver circuitry that operates at half swings between HIGH and MEDIUM or MEDIUM and LOW states, with charge from one driver circuitry used to power another, reducing power consumption by minimizing voltage swings across data read/write lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional communication lines are added to increase memory storage capacity, then the memory can store more data, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameter by operating driver circuitry at half-swings (MEDIUM state instead of full HIGH/LOW swings), which reduces the voltage difference across communication lines and thereby reduces power consumption while maintaining the ability to communicate data across the same number of lines
2Quantity of substance
If additional communication lines are added to increase memory storage capacity, then the memory can store more data, but capacitance between lines increases power usage
Solution Approach 1:
The patent reduces capacitance-related power loss by changing the voltage swing parameter to half-swings, which reduces the charge/discharge cycles of the line capacitance and thereby reduces energy loss
3Reliability
If full voltage swings (HIGH to LOW) are used for data communication, then data transmission is reliable, but power consumption is high
Solution Approach 1:
The patent introduces a MEDIUM state as an intermediary voltage level between HIGH and LOW, allowing driver circuitry to communicate data by swinging between MEDIUM and HIGH or MEDIUM and LOW, which reduces the voltage swing幅度 and power consumption while maintaining reliable data transmission through the intermediary voltage level
Data Source
AI summary
A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.