Tri-State Bus Circuit for Dual-Master Signal Isolation
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Solution Overview
Problem
In electronic circuits, particularly in the motor vehicle sector, the requirement for dual microprocessors to operate as masters and connect to slaves via a bus system poses challenges such as increased complexity and potential damage to components due to synchronized clock signals.
Innovation Solution
The implementation of tri-state gates at the outputs of the masters, which can act as either closed or open switches, controls the connection between the masters, preventing interference and allowing only one master to transmit signals at a time, thereby preventing component damage and eliminating the need for multi-master capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two microprocessors are provided as backup processors to improve system reliability, then system reliability is improved, but the complexity of the bus system increases and component damage may occur due to synchronized clock signals
Solution Approach 1:
Tri-state gates are introduced as intermediary components between the microprocessors and the bus system. These gates act as controlled switches that prevent direct connection conflicts while allowing reliable backup processor operation. The tri-state gates mediate the interaction between multiple masters and the bus, eliminating the need for complex arbitration logic in each processor.
2Reliability
If both microprocessors are made operable as masters to improve system reliability, then system reliability is improved, but component damage may occur due to clock signal interference
Solution Approach 1:
Tri-state gates serve as protective intermediaries that prevent harmful signal interference between masters. When one master is active, its tri-state gate is closed while the other master's gate is open, physically isolating the inactive master from the bus and preventing clock signal conflicts that could damage components.
Solution Approach 2:
The tri-state gates dynamically change their state (open/closed) based on which master is currently active. This dynamic switching allows both processors to be capable of master operation while ensuring that only one connects to the bus at any given time, preventing signal interference and component damage.
3Reliability
If multi-master capability is implemented in microprocessors to allow both to operate as masters, then system reliability is improved, but the effort and complexity required increases
Solution Approach 1:
The tri-state gates external to the processors serve as mediators that simplify the overall system implementation. Instead of requiring complex multi-master arbitration logic within each processor, the simple tri-state gate circuitry externally manages master access, reducing the implementation effort and complexity in the processors themselves while still enabling reliable dual-master operation.
Data Source
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Figure 2
Figure 3a~3b
AI summary
The invention relates to an electrical circuit (10) for transmitting signals between two masters (11, 12) and one or more slaves (13, 14). The two masters (11, 12) and the slave or slaves (13, 14) are interconnected by means of a bus system (15). At least one master data signal (MO) can be generated by each of the two masters (11, 12) and can be received by the slave or slaves (13, 14). A tri-state gate (16) is present at the outputs of the two masters (11, 12) at which the respective master data signal (MO) is present. The tri-state gates (16) act either as closed or as opened switches. The tri-state gates (16) are actuated such that tri-state gate (1611) associated with one of the two masters (11) acts as a closed switch and the tri-state gate (1612) associated with the other of the two masters (12) acts as an opened switch.