Tri-State Inverter Delay Tuning for Voltage Droop Detection
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Solution Overview
Problem
Existing droop detectors face challenges in accurately measuring voltage droops due to limitations in resolution, particularly in detecting small changes in output voltage during load variations or transient conditions.
Innovation Solution
The implementation of a circuit utilizing one or more tri-state inverters, which provide adjustable delay adjustments to the signal waveform, allowing for precise control of signal timing and resolution. This is achieved by determining the gate capacitance at a node between digital gates coupled to the tri-state inverters and adjusting the number of enabled tri-state inverters to achieve the desired delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional droop detectors are used to monitor output voltage changes, then the system can detect voltage droops during load variations, but the resolution is insufficient for accurately detecting small changes in output voltage
Solution Approach 1:
The patent segments the continuous voltage measurement function into discrete time samples using multiple switches (S1-S4) that sequentially connect different capacitor pairs (C1-C4, C5-C8) to the measurement node. This segmentation allows the system to capture voltage droop characteristics at multiple resolution levels by selecting different capacitor combinations, thereby improving measurement precision without requiring a single complex high-resolution detector circuit.
Solution Approach 2:
The patent introduces a temporal dimension to the voltage measurement by using sequential switching and time-based sampling. Instead of measuring voltage continuously with high precision, the system captures voltage droop information at discrete time points (t1, t2, t3, t4) and uses the time evolution of voltage samples to detect droop characteristics. This dimensional transformation allows standard precision measurements combined with temporal analysis to achieve effective high-resolution droop detection.
2Measurement precision
If the number of enabled tri-state inverters is increased to achieve finer delay adjustment, then the resolution of voltage droop detection is enhanced, but the device complexity increases
Solution Approach 1:
The patent divides the delay adjustment function into multiple discrete steps, each controlled by individual tri-state inverters (INV1-INV4). Each inverter provides a specific delay increment when enabled, allowing the total delay to be segmented into controllable units. This segmentation enables precise delay adjustment by selectively enabling combinations of inverters, achieving fine resolution without requiring a single complex continuous adjustment mechanism.
Solution Approach 2:
The patent employs dynamic control of tri-state inverters where each inverter can be independently enabled or disabled based on the desired delay setting. The dynamic switching of inverters allows the circuit to adaptively adjust delay in real-time, providing flexible and precise control. The tri-state nature of the inverters enables them to transition between active (providing delay) and high-impedance (not affecting circuit) states, facilitating dynamic resolution adjustment without permanent circuit modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the resolution of voltage droop detection, allowing for more precise measurement of small voltage changes, thereby improving the clarity and accuracy of droop detection in power supply systems.
Implementation Method 1
determining a first gate capacitance at a node between first and second digital gates coupled to one or more tri-state inverters; activating at least one of the one or more tri-state inverters; and determining a second gate capacitance at the node, wherein a difference between first and second gate capacitances corresponds to a delay adjustment of a signal waveform
Data Source
AI summary
According to one implementation, a circuit includes a first digital gate (108A) and a timing offset circuit portion (238) coupled to the first digital gate (108A) that includes one or more tri-state inverters (202A . . . 202N) where a capacitance at an output of the first digital gate (108A) is based on a quantity of enabled tri-state inverters of the one or more tri-state inverters (202A-202N).