Tri-State I/O Port Timing for Contention-Free Bus Switching
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Solution Overview
Problem
Conventional tri-state I/O ports require a turnaround time to prevent bus contention, which leads to power dissipation and unstable systems, but this solution decreases data transmission speed.
Innovation Solution
A tri-state I/O port design comprising a tri-state logic block, a weak buffer, and a delay block, where the weak buffer maintains output levels and the delay block turns off pull capabilities, eliminating the need for a turnaround time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a turnaround time is added to prevent bus contention, then bus stability is improved, but data transmission speed deteriorates
Solution Approach 1:
The patent applies preliminary action by proactively turning off the pull-up and pull-down transistors before bus mastering switches occur. The control circuit detects the output enable signal state changes and提前 disables the opposing drive's transistors, preventing bus contention before it can happen. This eliminates the need for turnaround time while maintaining bus stability.
2Productivity
If turnaround time is eliminated to increase data transmission speed, then productivity is improved, but bus contention and power dissipation occur
Solution Approach 1:
The patent implements feedback by using the output enable signal (OE) from each drive as input to the control circuit. The control circuit continuously monitors the OE signal state changes and uses this feedback to dynamically control the turn-off timing of pull-up and pull-down transistors, preventing bus contention while enabling continuous high-speed transmission.
Solution Approach 2:
The control circuit performs preliminary action by detecting OE signal transitions and提前 turning off the opposing drive's transistors before bus mastering switches occur. This proactive approach prevents bus contention and power dissipation while allowing immediate high-speed data transmission without turnaround time.
3Power
If multiple transistors are put in parallel to enhance pull-up and pull-down capability, then driving strength is improved, but power dissipation and risk of breakdown increase during bus contention
Solution Approach 1:
The patent applies preliminary anti-action by implementing a control circuit that detects OE signal transitions and preemptively turns off the pull-up and pull-down transistors of the drive that is about to lose bus mastering. This prevents bus contention before it occurs, protecting the parallel transistors from excessive current and power dissipation while maintaining their high driving strength during normal operation.
Data Source
AI summary
The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block.