Tri-transistor MTPROM Cell Architecture for High Density
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Solution Overview
Problem
Existing non-volatile memory cell architectures, such as the twin-transistor MTP memory, face challenges in achieving high density and sensing margin due to the need for a global reference wordline and sensitivity to device variation.
Innovation Solution
A memory cell architecture utilizing three connected transistors, where two transistors are programmable to store a first bit value and the third transistor is programmable to store a second bit value, with specific threshold voltage configurations to improve density and sensing margin, allowing for efficient storage of two bits of information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If twin-transistor MTP memory architecture is used, then sensing margin is improved, but device complexity increases due to need for global reference wordline
Solution Approach 1:
The patent merges the reference transistor function into the cell structure itself by using the second transistor to store the complement bit, eliminating the need for separate global reference wordlines. Each cell becomes self-contained with both data and reference functionality integrated into the same transistor pair.
Solution Approach 2:
The second transistor serves dual purposes: it stores the complement bit value while simultaneously acting as a localized reference for sensing operations. This multi-functional design eliminates the need for dedicated reference structures and global reference wordlines.
2Measurement precision
If twin-transistor MTP memory architecture is used, then sensing margin is improved, but manufacturing precision requirements increase due to sensitivity to device variation
Solution Approach 1:
The patent implements localized reference transistors within each cell rather than relying on global references. This local reference approach compensates for device variations specific to each cell, reducing sensitivity to manufacturing precision variations across the array.
Solution Approach 2:
The patent uses threshold voltage programming to create distinct voltage states in the transistors. By programming the first transistor with one threshold voltage state and the second with another, the system creates inherent differentiation that improves sensing margin while compensating for device variations.
3Area of stationary object
If higher density is achieved by using fewer transistors per bit, then area efficiency improves, but sensing margin deteriorates
Solution Approach 1:
The patent combines data storage and reference functionality into a single transistor pair, achieving 1 transistor per bit density while maintaining sensing margin. The same two transistors serve both to store the bit value and to provide the reference for sensing, eliminating the need for additional reference transistors.
Solution Approach 2:
Each transistor in the pair performs multiple functions: the first transistor stores the primary bit value while the second stores the complement and serves as a localized reference. This multi-functionality allows high density without sacrificing sensing performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tri-transistor architecture enhances memory cell density and sensing margin, improving upon existing designs by allowing for more efficient storage of two bits of information while maintaining adequate programming and sensing capabilities.
Implementation Method 1
a parameter, e.g., a transistor device threshold voltage, that may be varied for storing a desired information, e.g., by injecting charges into a floating gate or gate oxide
Implementation Method 2
This induces a Vt shift from its nominal value to a higher value due to BTI (Bias temperature instability) and HCI (hot carrier injection) effects
Implementation Method 3
This induces a Vt shift from its nominal value to a higher value due to BTI (Bias temperature instability) and HCI (hot carrier injection) effects
Data Source
AI summary
A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.