Triangular LED Pattern Array for Current Distribution
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Solution Overview
Problem
High-voltage LED devices with numerous bonding wires and complex circuits suffer from current density crowding and reduced photosynthetic efficiency due to auger recombination, necessitating a new design and process for improved manufacturing.
Innovation Solution
A method involving a substrate with sequential formation of N-GaN and P-GaN limiting layers, pattern isolation via photo lithography and etching, and connection of triangular pattern units for series or parallel LED chip formation, with insulation and current blocking layers to enhance light extraction and current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple LEDs are connected in series or parallel to prepare high-voltage LED device, then high-voltage LED device can be obtained, but the structure is provided with too many bonding wires, too much cost and too large area
Solution Approach 1:
The LED structure is segmented into multiple independent light-emitting units (first LED, second LED, third LED, fourth LED) that are formed separately on the substrate. Each unit has its own active region, contact structure, and electrode, allowing them to function as independent LEDs that can be connected in series or parallel configurations within a single integrated device structure.
Solution Approach 2:
Multiple LED units are merged into a single integrated high-voltage LED device by sharing common substrate, contact structures, and electrode arrangements. The first and second LEDs share contact structures 121 and 122, while the third and fourth LEDs share contact structures 123 and 124, reducing the total number of bonding wires and interconnections needed compared to separate LED devices.
2Power
If multiple LEDs are connected in series or parallel to prepare high-voltage LED device, then high-voltage LED device can be obtained, but too much cost and too large area
Solution Approach 1:
The device area is efficiently segmented by arranging multiple LED units in a compact layout on a single substrate. The independent contact structures for each LED unit are positioned to minimize spacing requirements, allowing dense packing of multiple functional units within a reduced overall device footprint compared to separate LED devices.
Solution Approach 2:
Multiple LED units are combined into a single integrated structure that occupies less total area than multiple separate LED devices would require. The shared substrate, contact structures, and electrode arrangements create a compact high-voltage LED device that reduces both material costs and device footprint.
3Power
If connected in series or parallel under large circuit condition, then high-voltage LED device can be obtained, but crowding effect of current density is prone to take place regionally because of auger recombination, causing the photosynthetic efficiency of LED declines linearly
Solution Approach 1:
The current path is segmented into multiple independent LED units with separate active regions and contact structures. This segmentation distributes the current flow across multiple parallel current paths, preventing current density crowding in any single region and reducing the impact of auger recombination effects on overall device efficiency.
Solution Approach 2:
Each LED unit is designed with optimized local structures including specific contact structure configurations (121, 122, 123, 124) and electrode arrangements that improve current distribution within each unit. The independent contact structures for each LED unit are positioned to optimize current injection and reduce localized current density effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method optimizes high-voltage LED structure, reducing leakage current and enhancing luminescent efficiency by improving current distribution and light extraction, while maintaining efficient electrical connectivity.
Implementation Method 1
isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process
Implementation Method 2
patterns are prepared as the mask by photo lithography, and the initial shape of pattern unit is formed with inductively coupled plasma etching equipment and/or strong acid corrosion, then the GaN layer without mask is etched to the substrate layer to realize the disconnection of each unit
Implementation Method 3
forming a N-GaN limiting layer, an epitaxial light-emitting layer and a P-GaN limiting layer on the substrate in sequence
Implementation Method 4
the nitride based LED for a new generation of solid state lighting source that is green and environmental protective
Data Source
AI summary
The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit; in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

