Triangular Pillar Bumps for Gold Material Reduction in Chip Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing material usage and cost of gold bumps in chip structures while maintaining effective contact area and pad identification for efficient chip testing and packaging.
Innovation Solution
The use of triangular or trapezoidal pillar-shaped bumps with directional characteristics on chip pads reduces material usage and cost, enabling easier pad identification and alignment during testing and packaging processes by alternating the shape and direction of bumps on odd and even pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rectangular pillar-shaped bumps are used to connect chip pads to carrier, then reliable electrical connection is achieved, but material usage and cost increase
Solution Approach 1:
The patent applies asymmetry by changing the bump shape from symmetric rectangular pillar to asymmetric triangular or trapezoidal pillars. This asymmetric geometry reduces the cross-sectional area and volume of gold material required while maintaining the essential electrical connection function. The directional characteristic of asymmetric shapes also provides pad identification capability.
Solution Approach 2:
The patent changes the geometric parameters of the bump structure by transitioning from rectangular to triangular/trapezoidal shapes. This parameter change optimizes the material volume while preserving the bonding region contact area, thereby reducing gold material consumption without compromising connection reliability.
2Ease of manufacture
If uniform bumps are used on all pads, then manufacturing simplicity is maintained, but pad identification becomes difficult
Solution Approach 1:
The patent uses asymmetric triangular or trapezoidal bump shapes with specific directional orientations to encode pad identification information. By alternating the direction or orientation of asymmetric bumps across different pad locations, the system provides visual or tactile cues for identifying specific pads during testing and packaging without requiring additional identification structures.
Solution Approach 2:
The patent applies local quality by giving different directional characteristics or orientations to bumps at different pad locations. This localized variation in bump orientation or shape direction provides spatial encoding information for pad identification while maintaining the same basic triangular/trapezoidal geometry for all bumps, balancing manufacturing simplicity with identification capability.
3Quantity of substance
If bump material usage is reduced to lower cost, then cost-benefit ratio improves, but contact area with carrier may be insufficient
Solution Approach 1:
The patent optimizes geometric parameters by transitioning from rectangular to triangular/trapezoidal bump shapes, which reduces the overall volume and cross-sectional area of material required. The design carefully controls the base width and height parameters to ensure adequate contact area with the carrier while minimizing total material consumption through the tapered geometry.
Solution Approach 2:
The patent addresses the contact area concern by utilizing the vertical dimension through the pillar height. By optimizing the height-to-base-area ratio, the design compensates for reduced cross-sectional area with increased vertical extent, maintaining sufficient bonding capacity and electrical contact while reducing lateral material usage.
Data Source
AI summary
A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers.