Triangular Ridge Epitaxial Silicon Channel for FET Driving Force
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Solution Overview
Problem
Miniaturization of semiconductor devices with field effect transistors (FETs) leads to reduced driving force and operation speed, and existing methods to enhance driving force, such as three-dimensional channel structures, face technical hurdles and limitations in achieving both miniaturization and improved cut-off characteristics.
Innovation Solution
A semiconductor device with a channel region comprising multiple projected epitaxial silicon regions arranged in a triangular ridge structure, which increases channel width and enhances current density, while maintaining miniaturization through a specific manufacturing process involving epitaxial growth and gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturization is pursued, then device size is reduced, but driving force and operation speed are reduced
Solution Approach 1:
The patent transitions from a planar two-dimensional channel structure to a three-dimensional structure with multiple projected epitaxial silicon regions arranged in the width direction. This dimensional change allows the channel width to be effectively increased while maintaining a compact device footprint, thereby preserving driving force during miniaturization
Solution Approach 2:
The channel region is segmented into multiple projected epitaxial silicon regions (first, second, third, and fourth regions) arranged in the width direction. Each region contributes to the overall channel width and current conduction path, allowing the total channel width to exceed the minimum design rule size without increasing the lateral device footprint
2Area of moving object
If three-dimensional channel structure is employed, then channel width is increased, but manufacturing complexity increases
Solution Approach 1:
The gate electrode is designed to function as a common gate for all multiple channel regions simultaneously. This multi-functional gate structure controls the electrical potential across all projected epitaxial silicon regions, enabling unified control of multiple channels without requiring separate gate structures for each region, thereby reducing manufacturing complexity
Solution Approach 2:
Adjacent channel regions share common source/drain regions and a common gate electrode. This merging of components reduces the total number of discrete elements that would need to be manufactured and assembled, simplifying the overall device structure and manufacturing process while maintaining increased channel width
3Power
If channel width is increased, then driving force is improved, but cut-off characteristics deteriorate
Solution Approach 1:
The patent creates different local geometries within the channel region by forming projected epitaxial silicon regions with specific ridge portions. These local structural variations enhance the electric field distribution and carrier confinement in specific areas, improving cut-off characteristics while maintaining overall increased channel width for driving force
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the driving force and cut-off characteristics of FETs by enhancing current density and reducing back gate effects, thereby improving the performance and responsiveness of semiconductor devices while maintaining miniaturization.
Implementation Method 1
the gate electrode adjusts an electrical potential of the channel region
Implementation Method 2
each of the projected epitaxial silicon regions having a triangular ridge portion arranged in a direction perpendicular to the width of the channel region
Data Source
AI summary
A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel region, each of the projected epitaxial silicon regions having a triangular ridge portion, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film.