Embedded Triangular SiGe Stressor for NMOS Electron Mobility
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Solution Overview
Problem
Current n-FET High-k/Metal-Gate technologies face challenges in enhancing electron mobility due to aggressive pitch and height scaling, limiting the effectiveness of stress liners in MOSFET structures, particularly in NMOS devices where embedded stress elements are difficult to integrate near the inversion layer.
Innovation Solution
The introduction of an embedded triangular-shaped silicon germanium (SiGe) stressor within the semiconductor substrate, formed through anisotropic etching and epitaxial growth, to create tensile stress in the channel region of NMOS devices, enhancing electron mobility and drive currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress liners are used to enhance electron mobility in NMOS devices, then carrier mobility is improved, but the effectiveness is limited due to aggressive pitch and height scaling
Solution Approach 1:
The patent transitions from surface-level stress liners to subsurface embedded stressors, moving the stress application from the vertical surface dimension to the horizontal subsurface dimension. This allows stress to be applied closer to the channel region without being constrained by surface topology and pitch scaling limitations.
Solution Approach 2:
The embedded stressors are formed prior to final device fabrication steps, with stress material deposited and patterned in advance. This preliminary action allows the stress structure to be established before subsequent processing, ensuring stress effectiveness is not compromised by later fabrication constraints.
2Reliability
If embedded stress elements are introduced near the inversion layer to enhance performance, then drive currents are improved, but process integration becomes more challenging
Solution Approach 1:
The patent combines multiple functions into the embedded stressor structure: stress application, spacer formation, and potential gate alignment reference. By merging these functions into a single integrated structure formed through coordinated deposition and etching steps, the complexity of separate processes is reduced.
Solution Approach 2:
The patent controls stressor depth, width, and material composition parameters to optimize stress delivery while maintaining compatibility with standard fabrication processes. By carefully adjusting these parameters, the stressor can be positioned near the inversion layer without requiring fundamentally new manufacturing capabilities.
3Ease of manufacture
If source and drain stressors are positioned away from the inversion layer to simplify fabrication, then manufacturing is easier, but stress effectiveness is reduced
Solution Approach 1:
The patent positions stressors in the horizontal subsurface dimension rather than only at vertical surface locations. This dimensional shift allows stressors to be placed laterally adjacent to and near the channel inversion layer, delivering stress directly to the active region while maintaining fabrication simplicity through planar processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The embedded SiGe stressor significantly increases stress levels in the channel region, improving electron mobility and drive currents beyond conventional technologies, as demonstrated by stress profile simulations and fabrication processes.
Implementation Method 1
stress may be introduced in the channel region of the MOSFET to improve carrier mobility
Implementation Method 2
formed through anisotropic etching and epitaxial growth
Implementation Method 3
formed through anisotropic etching and epitaxial growth
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.