Triangular Sidewall Spacers for Double Patterning
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Solution Overview
Problem
Current self-aligned double patterning (SADP) techniques for increasing feature density in semiconductor devices are cost-prohibitive and time-consuming due to complex spacer deposition processes and patterning difficulties caused by mandrel size limitations.
Innovation Solution
The method involves creating vertically tapered, rough triangular sidewall spacers with a pointed tip using a sacrificial layer and a hard mask, which are used to pattern semiconductor structures, allowing for increased feature density without the limitations of standard lithographic techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard self-aligned double patterning (SADP) techniques are used to increase feature density, then feature density is improved, but manufacturing cost and production cycle time increase significantly
Solution Approach 1:
The patent extracts and eliminates the mandrel formation step from the traditional SADP process. By directly forming triangular sidewall spacers without requiring mandrels, the method simplifies the manufacturing process while maintaining the ability to double feature density, thereby resolving the contradiction between feature density improvement and process complexity increase
Solution Approach 2:
The patent segments the spacer formation process into distinct vertical and lateral components. By creating triangular spacers with vertically tapered sidewalls through selective etching, the method achieves precise dimensional control without requiring complex mandrel structures, thus improving feature density while reducing process complexity
2Manufacturing precision
If standard SADP techniques are used to increase feature density, then feature density is improved, but production cycle time increases due to additional operations
Solution Approach 1:
The patent performs preliminary patterning of the sacrificial layer to create vertically tapered structures before spacer deposition. This preliminary action enables direct formation of triangular spacers without requiring subsequent mandrel removal steps, thereby reducing production cycle time while achieving the desired feature density
Solution Approach 2:
By removing the mandrel formation and removal operations from the process sequence, the patent directly forms triangular sidewall spacers in a single deposition and etch cycle. This extraction of unnecessary steps significantly reduces production cycle time while maintaining improved feature density
3Manufacturing precision
If standard SADP techniques are used, then feature density is improved, but patterning difficulties arise due to mandrel size limitations
Solution Approach 1:
Instead of forming spacers around mandrels (traditional approach), the patent inverts the process by directly etching triangular spacers from the sacrificial layer. This inversion eliminates mandrel size limitations and associated patterning difficulties, achieving improved feature density with enhanced manufacturing ease
Solution Approach 2:
By extracting the mandrel component from the process, the patent eliminates the fundamental physical limits of resolution that constrain mandrel-based approaches. The direct triangular spacer formation method achieves superior patterning ease while maintaining improved feature density
Data Source
AI summary
An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below.