Triangular Systolic Array Matrix Inversion
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Solution Overview
Problem
Current integrated circuit technologies face challenges in efficiently performing matrix inversion for massive MIMO systems, particularly in terms of computational complexity and resource utilization, especially when implemented on field programmable gate arrays (FPGAs), due to stringent throughput and latency requirements.
Innovation Solution
The implementation of a systolic array circuitry using triangular systolic arrays with multiplexer networks that directly route data between stages, eliminating the need for intermediate storage and utilizing idle processing elements as helpers to increase throughput and reduce resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional matrix inversion methods are used on FPGAs, then computational accuracy is maintained, but resource consumption and computational complexity increase significantly
Solution Approach 1:
The matrix inversion process is segmented into three distinct stages: Cholesky decomposition, triangular matrix inversion, and triangular matrix multiplication. Each stage is processed by dedicated processing elements in the systolic array, allowing parallel execution and reducing overall computational complexity while maintaining numerical stability through systematic decomposition of the inversion task
Solution Approach 2:
The systolic array introduces intermediate processing stages with dedicated buffer memory and multiplexer networks that mediate between input matrix data and final inversion results. These intermediaries enable pipelined processing and reduce the computational burden on individual processing elements while preserving numerical accuracy through controlled data flow
2Loss of information
If intermediate storage is used between processing stages, then data accuracy is preserved, but memory storage space and memory access operations increase
Solution Approach 1:
The output buffer memory is merged with the processing element array structure, allowing intermediate results to be stored in-place within the systolic array rather than in separate external memory. This integration reduces the total quantity of memory storage space required while maintaining data accuracy through controlled write-back operations
Solution Approach 2:
The systolic array performs self-service by routing intermediate results directly through multiplexer networks back to processing elements for subsequent operations. This self-contained data circulation eliminates the need for extensive external memory storage and access operations, reducing both memory space requirements and memory read/write overhead
3Productivity
If all processing elements are actively used, then processing throughput is maximized, but resource consumption increases
Solution Approach 1:
The systolic array implements dynamic resource allocation where processing elements transition between active computation modes and idle states based on the current processing stage. During Cholesky decomposition, only certain elements are active; during triangular inversion, different elements become active. This dynamic behavior allows the system to maintain high throughput while reducing average resource consumption across the entire array
Solution Approach 2:
Processing elements are designed with universal functionality to perform multiple operations: Cholesky decomposition, triangular matrix inversion, and triangular matrix multiplication. Each processing element can execute different computational tasks depending on the current stage, allowing the same physical resources to serve multiple purposes and reduce overall resource consumption while maintaining high processing throughput
Data Source
AI summary
Integrated circuit devices, methods, and circuitry for implementing and using a systolic array are provided. Such circuitry may include processing elements arranged in a triangular systolic array. The processing elements may receive an input matrix and perform Cholesky decomposition in a first stage, triangular matrix inversion in a second stage, and matrix multiplication in a third stage to produce an inverse of the input matrix as an output matrix.