Triaxial Through-Chip Connection via Annulus Trench Metalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current technologies face challenges in forming precise, repeatable, and cost-effective electrical connections through electronic chips, especially when vias are deep, narrow, or close together, and when high-frequency signals are involved, leading to issues with signal cross-talk, capacitance, and resistance.
Innovation Solution
A process involving etching an annulus trench in a semiconductor substrate, metalizing the perimeter walls, creating a via trench, and thinning the substrate to expose the metal, allowing for electrically conductive connections while maintaining isolation and controlling capacitance and resistance, enabling chip-to-chip connections with high aspect ratios and high-frequency signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vias are made deep and narrow to achieve high-density chip-to-chip connections, then connection density is improved, but manufacturing precision deteriorates due to difficulty in forming precise, repeatable connections
Solution Approach 1:
The via formation process is segmented into multiple steps: first forming a shallow via, then depositing insulating material, and finally forming the deep via through the insulating layer. This segmentation allows each step to be optimized independently, achieving both high connection density and manufacturing precision.
Solution Approach 2:
Insulating material is deposited in advance before forming the deep via. This preliminary action creates a controlled interface that enables precise via formation while maintaining electrical isolation, resolving the contradiction between via depth and manufacturing precision.
2Area of stationary object
If vias are placed close together to reduce chip area, then area efficiency is improved, but signal cross-talk increases
Solution Approach 1:
An insulating material layer is introduced as an intermediary between adjacent vias. This intermediary layer electrically isolates the vias, preventing signal cross-talk while allowing them to be placed close together for area efficiency.
3Length of stationary object
If conventional via processes are used to achieve deep connections, then connection depth is improved, but chip damage increases due to process incompatibility with formed IC chips
Solution Approach 1:
The via formation process is segmented so that deep vias are formed after the IC chip is complete, rather than during chip fabrication. This segmentation allows conventional deep via processes to be applied without damaging the formed chip, as the chip is already encapsulated and protected.
Solution Approach 2:
The IC chip is fully formed and protected with encapsulation layers before the deep via formation process begins. This preliminary protection prevents damage to the chip during the aggressive via etching and metalization processes.
4Reliability
If large pad drivers are used for chip-to-chip connections to ensure signal integrity, then signal reliability is improved, but power consumption increases
Solution Approach 1:
The insulating material layer acts as an intermediary that provides electrical isolation and controlled impedance matching. This allows smaller, lower-power pad drivers to be used while maintaining signal integrity through the via structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables deep, narrow, and repeatable electrical connections with controlled capacitance and resistance, facilitating chip stacking and high-speed signal transmission, reducing the need for wirebonds and allowing for mixed material technologies and design flexibility.
Implementation Method 1
making a length of the via trench electrically conductive... so that the metal on the outer perimeter side wall and on the inner perimeter side wall are both electrically separated from each other and from the electrically conductive material
Data Source
AI summary
A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.