Trie Memory Compression via Reduced Cell Zones
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Solution Overview
Problem
Existing TRIE memory systems face inefficiencies in memory occupancy and processing speed due to the large number of empty cells, which complicates hardware implementation and reduces processing speed, especially as the size of analyzed sections increases.
Innovation Solution
A TRIE memory device that uses a method combining elements of width and path compression, where nodes with only one valid child can point to a reduced zone of one or two cells instead of a full register of 2K cells, optimizing memory usage and allowing for faster processing without exponential complexity increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a full register of 2K cells is used for each node in the TRIE memory, then the memory can accommodate all possible section values, but the number of empty cells increases significantly, reducing memory occupancy efficiency
Solution Approach 1:
The patent segments the memory structure into multiple stages, where each stage contains only the necessary memory cells for that level of the TRIE tree. Instead of using full 2K-cell registers at every node, the memory is divided into stages with varying numbers of cells based on the actual data distribution, eliminating empty cells and improving occupancy efficiency.
Solution Approach 2:
The patent introduces a new dimension to the traditional TRIE memory by adding a stage index dimension. Memory cells are organized as T[i,j] where i represents the stage and j represents the cell position within that stage. This dimensional reorganization allows the memory to adapt its structure to the actual data patterns, using only necessary cells at each stage rather than fixed full registers.
2Productivity
If the size of analyzed sections (K bits) increases, then more data can be processed per section, but the memory size and processing complexity increase exponentially
Solution Approach 1:
The patent makes the memory structure dynamic by allowing the number of cells per stage to be determined by the actual data patterns rather than being fixed at 2K. The memory adapts its configuration based on the specific TRIE tree being implemented, enabling efficient handling of different section sizes without exponential complexity increases.
Solution Approach 2:
The patent changes the fundamental parameter of memory cell organization from fixed 2K-cell registers to variable-size stages. By changing how memory is parameterized and organized, the system can handle larger section sizes efficiently, processing more data per section while avoiding exponential complexity growth through adaptive memory allocation.
3Speed
If the TRIE memory is optimized for high-speed processing, then data string analysis speed increases, but memory occupancy is reduced due to the need for faster access structures
Solution Approach 1:
The patent performs preliminary organization of memory cells into stages based on the TRIE tree structure before data processing begins. This preliminary action optimizes the memory layout for high-speed access patterns, arranging cells in a way that enables fast traversal while maintaining high occupancy by including only necessary cells at each stage.
Data Source
AI summary
The invention relates to a tri-type memory device comprising a compression mechanism. According to the invention, the memory stores binary patterns that are associated with respective references. Data chains are analyzed by successive section of K bits (K>1) in order to extract one of the references when there is a match with a stored binary pattern associated with said reference. The memory is organized into several successive memory cell states, the analysis of the (i+1)-th section of a chain providing access to a cell of stage i≧0. Each non-empty cell of a stage i≧0 contains one of the following: a register-type analysis tracking pointer designating a register of 2K cells of stage i+1; a linear-type analysis tracking pointer designating a zone of one or two cells forming a reduced register of stage i+1; or a reference associated with a stored binary pattern.