Trie Node Bitmaps for Longest Prefix Matching Speed
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Solution Overview
Problem
Current methods for longest prefix matching in routers, such as those using compressed multi-bit tries, fail to achieve sufficient search speed to support high interface rates and large routing tables, leading to inefficiencies in processing and memory usage.
Innovation Solution
The method employs a trie-based approach with enhanced node structures, including child and type bitmaps, and internal bitmaps to process r+1 bits of the search keyword at a time, allowing for faster search operations by optimizing memory access and reducing unnecessary data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a compressed multi-bit trie is used for longest prefix matching, then storage space is saved and the structure is compact, but the search speed is limited because only r bits can be read at a time which cannot satisfy the requirement of continuously growing line rates
Solution Approach 1:
The patent segments the routing table into multiple levels (L0, L1, L2, etc.) with each level containing trie nodes that store prefixes of increasing length. This hierarchical segmentation allows the system to process r+1 bits at each level while maintaining manageable node structures, resolving the contradiction between search speed and device complexity by distributing the search workload across multiple organized levels rather than requiring a single complex structure
Solution Approach 2:
The patent adds a vertical dimension to the traditional horizontal trie structure by organizing nodes into multiple levels where each level processes additional bits. This dimensional transformation enables processing of r+1 bits per node read while maintaining node complexity within acceptable bounds, as each node only needs to handle its specific level's bit processing rather than the entire prefix length
2Speed
If SRAM is used to realize high speed search, then search speed is improved, but it cannot support a large-sized routing table
Solution Approach 1:
The patent segments the large routing table into multiple levels where L0 contains nodes for the first r bits, L1 contains nodes for bits r+1 to 2r, and so on. This segmentation allows the system to use smaller, faster memory structures at each level while collectively supporting a large routing table capacity, resolving the contradiction between search speed and routing table size by distributing data across multiple manageable segments
Solution Approach 2:
The patent transforms the single-dimension memory access problem into a multi-dimensional solution by organizing routing data across multiple levels. Each level can be implemented in faster memory, and the hierarchical structure allows the system to support large routing tables by distributing entries across levels rather than requiring a single large memory structure, thus resolving the speed-capacity contradiction
3Quantity of substance
If DRAM is used to support a large-sized routing table, then routing table capacity is improved, but search speed is reduced due to the low rate of the DRAM
Solution Approach 1:
The patent segments the routing table search into multiple sequential steps, where each step processes a portion of the prefix (r+1 bits per level). This segmentation allows the use of DRAM for storing the complete large routing table while maintaining acceptable search speeds by processing smaller chunks of data at each memory access, resolving the contradiction between capacity and speed by breaking the search into manageable segments
Solution Approach 2:
The patent performs preliminary organization of routing data into a hierarchical structure before the actual search operation. By pre-organizing prefixes into levels L0, L1, L2 with increasing prefix lengths, the system prepares the data in advance so that during search, only relevant portions need to be accessed from DRAM, thus mitigating the speed limitation of DRAM while maintaining large routing table capacity
Data Source
AI summary
The present invention discloses a method and apparatus for longest prefix matching. The method includes (A) reading a current-level trie node (TNODE) in the trie, (B) determining whether an offset field of the TNODE indicates that a matched prefix exists in an upper level node and, if so, adding the offset field of the TNODE to a pointer that points to a leaf array in the upper level node, updating a current best match pointer with the computation result and executing block (C), otherwise, executing block (C), (C) determining whether the TNODE has a child node according to a child bitmap, when it is determined that a branch flag of the TNODE matches a corresponding bit of a search keyword, and (D) when it is determined that the TNODE has no child node, reading the internal bitmap of the TNODE, computing a longest matched prefix in the TNODE according to the internal bitmap and a pointer that points to a leaf array in the TNODE, updating the current best match pointer with the computation result, and computing an address of a leaf node (LNODE) associated with the current best match pointer.