Trig Modulation ESD Protection Device for Low Trigger Voltage
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Solution Overview
Problem
Conventional high voltage electrostatic discharge (ESD) protection devices face challenges in maintaining a holding voltage higher than the operation voltage without increasing the trigger voltage, leading to potential device damage or latch-up, and existing methods to reduce trigger voltage, such as increasing base-emitter resistance, are ineffective and increase layout area, hindering device integration.
Innovation Solution
A trig modulation ESD protection device is designed by separating the source of the NMOS transistor from the bulk and creating a parasitic PMOS transistor to modulate the base-emitter resistance of the parasitic BJT device, comprising a semiconductor substrate with specific doped regions and gates configured to control the trigger voltage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the holding voltage is increased to be higher than the operation voltage, then the ESD protection capability is improved, but the trigger voltage is also increased which may cause device damage or latch-up
Solution Approach 1:
The device is segmented into multiple functional regions including a first transistor (NMOS) for ESD protection, a second transistor (PMOS) for trig modulation, and associated doped regions. This segmentation allows independent optimization of holding voltage and trigger voltage characteristics, resolving the contradiction between ESD protection capability and trigger voltage level.
Solution Approach 2:
The patent implements dynamic control of the base-emitter resistance through the parasitic PMOS transistor that is modulated by the capacitor-resistor network. This dynamic adjustment allows the device to maintain high holding voltage while keeping trigger voltage low, as the resistance can adapt during different operational phases rather than being fixed.
2Object-affected harmful factors
If the base-emitter resistance is increased to reduce trigger voltage, then the trigger voltage is reduced, but the layout area is increased which hinders device integration
Solution Approach 1:
The patent merges the ESD protection function with a trig modulation function by integrating a second transistor (PMOS) and a capacitor-resistor network into the conventional ESD structure. This combination allows the base-emitter resistance to be modulated dynamically without requiring additional layout area for separate resistance increase, as the modulation is achieved through the coupled transistor-action rather than physical separation.
Solution Approach 2:
The patent changes the electrical parameters of the device by introducing a parasitic PMOS transistor that actively modulates the base-emitter resistance. Instead of increasing the physical distance between source and bulk (which increases area), the resistance is reduced through electrical parameter control via the PMOS transistor and RC network, maintaining compact layout while achieving low trigger voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the trigger voltage while maintaining a higher holding voltage, enhancing ESD protection without increasing the device layout area, thus enabling miniaturization and integration of ESD protection devices.
Implementation Method 1
a first gate electrically coupled to a first end of a capacitor and a second of a resistor
Implementation Method 2
modulate the base-emitter resistance of the parasitic BJT device
Implementation Method 3
specific doped regions and gates configured to control the trigger voltage effectively
Data Source
AI summary
Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.