Tri-Gate Transistor Fin Formation on Bulk Substrate
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Solution Overview
Problem
Conventional FinFET and tri-gate transistor architectures face limitations due to high series resistance and drive current limitations, particularly in bulk configurations, which hinder their competitiveness with standard planar transistor architectures.
Innovation Solution
The formation of double gate or tri-gate transistors on a silicon bulk substrate using well-established two-dimensional process techniques, which includes forming fins with increased silicon volume and self-aligned gate electrode structures, reduces series resistance and enhances manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If conventional FinFET and tri-gate transistor architectures are used on bulk substrates, then three-dimensional transistor configurations are achieved, but high series resistance and drive current limitations occur
Solution Approach 1:
The patent transitions from planar two-dimensional transistor architectures to three-dimensional FinFET and tri-gate configurations by forming fins that extend vertically from the bulk substrate. This dimensional change increases the effective channel width while maintaining control over the channel, thereby improving drive current capability without sacrificing the three-dimensional structure. The fin height and width are carefully controlled to optimize both the three-dimensional configuration benefits and series resistance characteristics.
2Speed
If channel length is decreased to improve switching speed, then high speed performance is achieved, but leakage current increases exponentially
Solution Approach 1:
The patent employs three-dimensional FinFET and tri-gate structures where the gate wraps around the fin channel, providing superior electrostatic control compared to planar devices. This enhanced control allows for shorter channel lengths that maintain low leakage current by preventing direct tunneling and short-channel effects. The vertical fin structure and wrapped gate configuration enable aggressive scaling while maintaining acceptable leakage characteristics.
Solution Approach 2:
The patent utilizes composite material structures including high-k dielectric materials combined with metal gate electrodes in the tri-gate configuration. This composite approach enables better control of the electric field in the channel, improving switching speed while suppressing leakage current through enhanced gate control and reduced oxide thickness requirements.
3Power
If ultra-thin silicon dioxide gate insulation layer is used to provide required capacitance, then capacitive coupling is enhanced, but direct tunneling leakage increases
Solution Approach 1:
The patent changes the dielectric parameter by transitioning from silicon dioxide to high-k dielectric materials. This parameter change allows for physically thicker gate insulation layers that provide the same or higher capacitive coupling while preventing direct tunneling leakage. The high-k material's superior dielectric constant enables maintaining required capacitance values without the harmful effects of ultra-thin oxide layers.
Solution Approach 2:
The patent employs composite gate stack structures combining high-k dielectric materials with metal gate electrodes. This composite material approach provides both the required capacitive coupling for high-speed operation and suppression of tunneling leakage through the superior dielectric properties of the high-k material, while the metal gate enables precise threshold voltage control.
4Productivity
If well-established two-dimensional process techniques are used after fin formation, then manufacturing efficiency is improved, but complex epitaxial growth processes are avoided
Solution Approach 1:
The patent performs preliminary fin formation and self-aligned gate electrode structure creation before applying standard two-dimensional processing techniques. This preliminary three-dimensional structuring enables subsequent planar processes to be used effectively, avoiding the need for complex epitaxial growth while maintaining manufacturing efficiency. The self-aligned structures are prepared in advance to guide subsequent simpler processing steps.
Solution Approach 2:
The patent forms three-dimensional fins and self-aligned gate structures as preliminary steps, then transitions to two-dimensional planar processing techniques for subsequent manufacturing steps. This approach leverages the benefits of three-dimensional architecture while utilizing the efficiency and simplicity of established two-dimensional processes, avoiding complex epitaxial growth requirements.
Data Source
AI summary
Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.