Tri-Gate Transistor Metal Gate Thickness Variation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Tri-gate transistors face issues with electric field concentration at the intersection of the sidewall and upper surface of fin-type active regions, leading to higher threshold voltage and degraded reliability of the gate dielectric layer due to self-heating and time-dependent dielectric breakdown.
Innovation Solution
The semiconductor device employs a gate dielectric layer with varying thicknesses of metal gate electrodes on the upper surfaces and sidewalls of fin active regions, where the thicknesses are strategically adjusted to reduce electric field concentration, using materials like titanium nitride and titanium aluminum carbon compounds, and incorporating a high-k dielectric layer to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a tri-gate transistor with fin-type active region is used to improve current-drive performance, then the transistor's current-drive performance is improved, but electric field concentration occurs at the intersection of sidewall and upper surface leading to higher threshold voltage and degraded gate dielectric reliability
Solution Approach 1:
The patent applies local quality by varying the metal gate electrode thickness at different locations: thinner at the upper surface and thicker at the sidewall intersection region. This non-uniform thickness distribution locally adjusts the electric field characteristics at the critical intersection area, reducing field concentration and self-heating effects while maintaining the tri-gate structure's current-drive performance advantage
Solution Approach 2:
The patent changes the physical parameter of gate electrode thickness from uniform to non-uniform distribution. Specifically, the metal gate electrode thickness is reduced at the upper surface compared to the sidewall region, thereby modifying the electric field distribution pattern and reducing the harmful concentration effect at the intersection without sacrificing the overall transistor performance
2Reliability
If metal gate electrode thickness is increased to reduce electric field concentration, then electric field concentration is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements parameter changes by controlling the metal gate electrode thickness to vary continuously or step-wise across different regions. This is achieved through controlled deposition processes that naturally form thinner layers at upper surfaces and thicker layers at sidewalls, or through selective etching processes, thereby managing electric field distribution without requiring complex multi-layer structures
Data Source
AI summary
A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.