Tri-gate SRAM with Independent Source and Drain Engineering
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Solution Overview
Problem
Intrinsic threshold voltage variations in smaller transistor geometries affect the static noise margin of CMOS SRAM cells, limiting the scaling of supply voltage and transistor size, and thus the yield of high-performance CMOS devices like ASICs and microprocessors due to die size and cost constraints.
Innovation Solution
The use of tri-gate transistors with independent source-and-drain sections and epitaxial growth to enhance conductivity, allowing for a higher cell ratio in SRAM cells without increasing layout size, achieved through specific processing steps including the formation of fin-shaped diffusions, shallow-trench isolation, and differentiated epitaxial films for pull-down and access regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor geometry is scaled down to smaller sizes, then device density and integration are improved, but intrinsic threshold voltage variations increase and static noise margin deteriorates
Solution Approach 1:
The patent transitions from planar 2D transistor channels to three-dimensional tri-gate structures, where the channel is formed at the intersection of three gates. This vertical dimensionality increase provides better gate control over the channel, reducing threshold voltage variations and improving static noise margin while maintaining small footprint area.
Solution Approach 2:
The patent implements independent source and drain engineering with different doping concentrations and epitaxial growth conditions for source and drain regions. This local differentiation optimizes carrier injection at the source and extraction at the drain, improving transistor performance and reducing variability without increasing overall device area.
2Use of energy by moving object
If supply voltage Vcc is scaled to lower voltage, then power consumption is reduced, but static noise margin is further reduced
Solution Approach 1:
The patent changes the physical parameters of the transistor structure by introducing tri-gate geometry and independent source/drain engineering, which fundamentally alter the electrical characteristics. These structural parameter changes enable maintaining adequate static noise margin even at reduced supply voltages by improving gate control and reducing threshold voltage variations.
3Ease of manufacture
If conventional 6T SRAM cell design is used, then manufacturing simplicity is maintained, but yield is limited due to intrinsic Vt variations
Solution Approach 1:
The patent segments the source and drain regions into independently engineered structures with separate epitaxial growth and doping processes. This segmentation allows independent optimization of source and drain characteristics, reducing threshold voltage variations and improving yield while maintaining compatibility with standard CMOS manufacturing flows.
4Reliability
If tri-gate transistors with independent source and drain are implemented, then cell ratio and conductivity are improved, but device complexity increases
Solution Approach 1:
The tri-gate structure serves multiple functions simultaneously: it provides enhanced gate control, defines the channel region, and enables independent source/drain engineering. This multi-functionality achieves improved cell ratio and conductivity without proportionally increasing device complexity, as the same structural elements perform multiple roles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the beta ratio and reduces external resistivity of pull-down regions compared to access regions, enhancing the cell ratio and overall conductivity without increasing layout size, thereby overcoming the limitations imposed by intrinsic threshold voltage variations.
Implementation Method 1
growing at least one epitaxy structure from an exposed portion of the active pattern
Data Source
Figure 1
Figure 2~2c
Figure 2d~3
AI summary
A static random-access memory (SRAM) circuit includes at least one access device on a first N-type fin (222) including source and drain sections for a pass region, at least one pull-up device on a P-type fin (226), and at least one pull-down device on a second N-type fin (222) including source-and-drain sections for a pull-down region. The SRAM circuit further comprises epitaxial structures (230, 236) on the source and drain sections of the pass and the pull-down devices, wherein the volume of the epitaxial structures on the source section and the drain section of the pass device (230) differs from the volume of the epitaxial structures on the source and drain section of the pull-down device (236) such that the external resistivity (Rext) for the pull-down region is lower than Rext for the pass region.