Tri-Gate Transistor Source Line Pull-Down for Memory Arrays
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Solution Overview
Problem
Conventional power-on-reset cells in non-volatile memory arrays have limited drive current, affecting read margin and area efficiency, and can disturb programming operations.
Innovation Solution
The use of transistor devices with specific doped regions and dielectric barriers in memory arrays as source line pull down devices, which increase drive current while minimizing area usage and reducing programming disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power-on-reset cells are used as source line pull down cells, then the memory array can perform source line voltage pulling, but the drive current is limited and read margin is affected
Solution Approach 1:
The patent changes the structural parameters of the pull-down device by transitioning from a conventional single-select-gate transistor to a tri-gate transistor device with three doped regions and three select gates. This parameter change enables the device to provide significantly higher drive current while maintaining proper voltage pulling functionality, thereby improving read margin without sacrificing reliability.
Solution Approach 2:
The invention segments the pull-down device into three separate select gates (first, second, and third select gates) controlling three doped regions, rather than using a single select gate. This segmentation allows independent control of current flow paths and enables the device to achieve higher drive current capability while maintaining the ability to perform source line voltage pulling reliably.
2Power
If more source line pull down cells are introduced to increase drive current, then drive current increases, but memory array area is consumed
Solution Approach 1:
The patent merges multiple transistor functions into a single tri-gate transistor device structure. By combining three select gates and three doped regions into one integrated device, the invention achieves high drive current capability equivalent to multiple separate pull-down cells while occupying the area of only one cell, thus resolving the area consumption problem.
Solution Approach 2:
The tri-gate transistor device serves multiple functions simultaneously: it acts as a source line pull-down device, provides high drive current, and maintains proper voltage control. This multi-functionality eliminates the need for additional dedicated pull-down cells, thereby preserving memory array area while achieving the desired drive current.
3Power
If power-on-reset cells are used as source line pull down cells, then source line voltage pulling is achieved, but programming operations of memory cells are disturbed
Solution Approach 1:
The patent applies local quality control by providing three separate select gates that can independently control current flow through different doped regions. This localized control allows the pull-down device to activate only specific current paths as needed, preventing unwanted interference with memory cell programming operations while maintaining effective source line voltage pulling capability.
Data Source
AI summary
In a non-limiting embodiment, a memory array is provided having a transistor device. The transistor device includes transistor device first, second and third doped regions in a substrate. The transistor device further includes a first transistor device select gate over a region between the transistor device first doped region and the transistor device second doped region, and a second transistor device select gate over a region between the transistor device first doped region and the transistor device third doped region. The transistor device further includes a transistor device dielectric barrier extending between the first transistor device select gate and the second transistor device select gate. A width of the dielectric barrier compared to a width of the first transistor device select gate and/or the second transistor device select gate may have a ratio ranging from 0.33:1 to 5:1.