Trigger Circuit Duty Cycle Control for Low-Power Gray Scale Display
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Solution Overview
Problem
The existing Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) driving modes for display technologies suffer from high power consumption, heat generation, complexity, and inability to achieve low gray scale display, hindering advancements such as high PPI and narrow bezel designs.
Innovation Solution
A trigger circuit with an input, reset, control, and duty cycle adjustment sub-circuit that adjusts the duty cycle of a clock signal, incorporating transistors and capacitors to control the brightness of a light emitting device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If PAM driving mode is used for gray scale display, then the driving circuit is simple, but power consumption is high and heat generation is great
Solution Approach 1:
The patent employs PWM (Pulse Width Modulation) periodic signaling to control the light emitting device, where the duty cycle of periodic pulses determines the gray scale level. This periodic action allows the device to remain either fully on or fully off during each pulse, minimizing power consumption while achieving variable brightness through temporal averaging.
Solution Approach 2:
The patent introduces a dynamic duty cycle adjustment mechanism that modifies the width of periodic pulses based on desired gray scale levels. By dynamically changing the pulse width ratio (duty cycle) while maintaining periodic operation, the system achieves variable brightness control without requiring the device to operate in intermediate high-power states.
2Use of energy by moving object
If PWM driving mode is introduced for gray scale display, then power consumption is reduced, but driving circuit complexity increases
Solution Approach 1:
The patent merges the gray scale control function directly into the existing PWM trigger circuit by adding a duty cycle adjustment sub-circuit that modifies the clock signal generation. This integration approach combines multiple functions (timing control, gray scale modulation, and signal generation) into a unified circuit architecture, reducing overall system complexity compared to separate control mechanisms.
Solution Approach 2:
The trigger circuit is designed with multi-functionality, where the same circuit structure handles both the timing control and gray scale modulation through duty cycle adjustment. The duty cycle adjustment sub-circuit serves multiple purposes: controlling pulse width, setting gray scale levels, and maintaining synchronization, thereby eliminating the need for additional dedicated control circuits.
3Measurement precision
If full-screen PWM driving mode is used, then low gray scale display is achieved, but power consumption remains high and heat generation increases
Solution Approach 1:
The patent applies periodic PWM pulses at high frequency to achieve gray scale display, where the light emitting device is switched fully on or off during each pulse cycle. The human eye's persistence of vision integrates these rapid on-off cycles into perceived intermediate brightness levels, enabling precise gray scale control without sustaining high power consumption during the entire display period.
Solution Approach 2:
The patent implements dynamic duty cycle modulation where the ratio of pulse-on time to total pulse period varies according to the desired gray scale level. This dynamic adjustment allows precise control of average power delivery to the light emitting device, achieving low gray scale levels with minimal power consumption while maintaining the ability to display across the full gray scale range.
Data Source
AI summary
A trigger circuit includes: an input sub-circuit, a reset sub-circuit, a control sub-circuit, a duty cycle adjustment sub-circuit and an output sub-circuit. The input sub-circuit controls a signal output terminal of the output sub-circuit to output a first power voltage or a second power voltage in response to an input control signal; the reset sub-circuit resets, in response to a reset signal, a first node through the reset signal, the first node being a connection node between the control sub-circuit and the duty cycle adjustment sub-circuit; the control sub-circuit controls a potential at the first node in response to a data voltage control signal; the duty cycle adjustment sub-circuit adjusts a duty cycle of a clock signal output from the signal output terminal in response to the potential at the first node, a potential of the clock signal jumps between the first power voltage and the second power voltage.