Trigger Ordering for Trace Streams in DSP Debug
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Solution Overview
Problem
Highly integrated digital signal processing systems face challenges in testability, observability, and controllability due to denser designs and increasing clock rates, leading to reduced visibility and control, longer design cycles, and increased costs, with traditional debug methods becoming inadequate for complex systems-on-a-chip.
Innovation Solution
The implementation of on-chip debug facilities with configurable emulation capabilities, including real-time emulation, advanced analysis, and trace functions, which allow for customizable debug resources and scalable solutions to balance time-to-market and cost needs, utilizing a two-tiered approach with integrated mega-modules and additional peripherals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple trace triggers are generated simultaneously in highly integrated digital signal processing systems, then comprehensive system activity monitoring is achieved, but trigger ordering ambiguities and unpredictable behavior occur
Solution Approach 1:
The patent applies preliminary action by establishing a fixed trigger ordering scheme before multiple triggers are generated simultaneously. The system pre-defines the execution sequence based on trigger identification values, ensuring that even when triggers occur at the same time, their execution order is predetermined and predictable. This resolves the contradiction by preparing the ordering rule in advance, eliminating runtime ambiguity.
Solution Approach 2:
The patent utilizes parameter changes by assigning different identification values to multiple triggers and using these parameters to determine execution order. When multiple triggers are generated simultaneously, the system compares their identification values and executes them in ascending order. This parameter-based ordering mechanism maintains measurement precision while ensuring reliable and predictable trigger behavior.
2Measurement precision
If on-chip debug facilities are implemented with configurable emulation capabilities, then visibility and control over system activity are enhanced, but device complexity and design costs increase
Solution Approach 1:
The patent applies universality by designing a unified trigger handling mechanism that manages multiple trace triggers with different identification values through a single standardized process. The same ordering logic and execution framework handle all triggers regardless of their source or type, reducing the need for separate complex handling circuits for each trigger type. This multi-functional approach enhances visibility and control while limiting the increase in device complexity.
Solution Approach 2:
The patent applies segmentation by dividing the trigger handling process into distinct stages: trigger generation, identification value assignment, ordering determination, and sequential execution. This segmented approach allows each component to be independently optimized and managed, making the overall debug facility more manageable and less complex while maintaining high visibility and control capabilities.
3Ease of manufacture
If traditional debug methods are used for complex systems-on-a-chip, then implementation simplicity is maintained, but detectable fault coverage and debug effectiveness become inadequate
Solution Approach 1:
The patent introduces an intermediary mechanism - the trigger ordering scheme based on identification values - that bridges the gap between simple traditional debug methods and the need for comprehensive fault coverage. This intermediary layer processes multiple triggers systematically, enabling enhanced debug effectiveness and fault detection while building upon the familiar framework of traditional debug approaches, thus maintaining relative implementation simplicity.
Data Source
AI summary
In the case of tracing processor activity and generating data streams multiple triggers can be generated at the same time. The issue is further complicated in a protected pipeline where certain locations are considered as in illegal instruction boundary. During those cycles certain information is invalid and cannot be transmitted to the user. Thus a received trace trigger cannot begin. This invention resolves all ambiguities related to multiple triggers so that the user has a known predictable behavior based on the setup of the triggers.