Triggered Data Generator with Stable Serial Output Timing
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Solution Overview
Problem
Conventional data generators experience significant time fluctuation, or jitter, from trigger arrival to substantial data output start due to the long period of the divided clock, which affects the reliability and stability of circuit operations, especially at increased clock speeds.
Innovation Solution
A data generator design that includes a memory with a first clock for reading parallel data, an address generating means, a delaying means, a counting means, a latch means, and a data rearranging means to produce rearranged parallel data, which is then converted to serial data, ensuring a constant time difference between trigger arrival and data output start, and allowing continuous operation before the trigger signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a divided clock with long period is used for parallel to serial conversion, then the conversion can be completed, but the time fluctuation from trigger arrival to data output start increases significantly
Solution Approach 1:
The patent applies preliminary action by continuously reading data from memory into a buffer before the trigger signal arrives. The address generator continuously increments addresses and loads data into the buffer in advance, so that when the trigger arrives, the data is already prepared and only needs to be latched and output. This eliminates the waiting time and fluctuation that would occur if data reading started after trigger arrival.
Solution Approach 2:
The patent implements dynamics by using a trigger-responsive latch that dynamically selects and outputs data from the buffer based on the trigger signal timing. The latch captures the counted number from the counter at the moment of trigger arrival and uses it to select the appropriate data from the buffer, ensuring that data output timing is precisely controlled relative to the trigger regardless of when the trigger occurs within the clock cycle.
2Reliability
If clock gating is used to enable clock after trigger signal, then the clock phase delay is removed, but the clock cannot be continuously provided preventing DLL usage
Solution Approach 1:
The patent segments the clock system into two independent parts: a continuously running clock that drives the address generator and buffer loading, and a trigger-gated clock that drives the latch and output stage. This segmentation allows the first clock to operate continuously enabling DLL usage for phase stability, while the second clock is properly gated by the trigger signal to control data output timing without conflict.
3Productivity
If continuous operation before trigger is implemented, then circuit speed is improved, but data output timing relative to trigger becomes uncertain
Solution Approach 1:
The patent implements feedback by using a counter that continuously counts clock cycles and a latch that captures this counted number at the moment of trigger arrival. The captured counted number is then used to control the data selection in the buffer, creating a feedback loop that automatically adjusts the data output timing based on when the trigger occurred. This ensures that even though data reading continues before the trigger, the final data output is precisely timed relative to the trigger signal.
Data Source
AI summary
A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing the address after the trigger signal. A hexadecimal counter counts a clock that is faster than the divided clock as the counted number circulates every one period of the divided clock . A trigger information latch latches the counted number of the counter when the trigger signal arrives and provides it to a MUX. The MUX selects data in a pair of the parallel data provided at first and second inputs I1 and I2 to produce rearranged parallel data bits according to the latched counted number. A parallel to serial converter receives the rearranged parallel data to convert it to serial data according to the clock.