Triggered Memory Mapped Access for Efficient Trace Data Collection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Developers face challenges in accessing and analyzing debug events on processors, particularly in retrieving trace data efficiently, which is crucial for debugging and performance assessment in systems like automotive powertrains and control applications, due to limitations in existing debug/trace interface standards.
Innovation Solution
A triggered memory mapped access system is introduced, which allows for event-triggered trace data collection through a memory mapped access mechanism, enabling read, write, and fetch transactions without disrupting system operation, and supports various trace messages compliant with the Nexus standard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional debug/trace interface standards are used, then developers can access processor debug events, but the access efficiency is limited and system operation is disrupted
Solution Approach 1:
The debug/trace system is segmented into independent functional units including a trace message generator, event trigger detector, and memory-mapped access interface. This segmentation allows trace data collection to occur independently from main processor operations, improving efficiency without disrupting system operation.
Solution Approach 2:
A memory-mapped access mechanism serves as an intermediary between the processor and debug tools. This intermediary enables efficient trace data collection by providing a dedicated communication channel that does not interfere with normal processor execution, thus improving productivity while maintaining system operation.
2Extent of automation
If existing debug interface standards are used, then basic debug functionality is provided, but real-time trace message generation is not achieved
Solution Approach 1:
The system performs preliminary actions by pre-configuring memory-mapped access addresses and event trigger conditions before processor execution. This allows real-time trace message generation to occur automatically without complex runtime processing, achieving automation while keeping the system relatively simple.
Solution Approach 2:
The trace message generator automatically detects event triggers and generates trace messages without external intervention. This self-service mechanism achieves real-time automated tracing while minimizing the complexity of external control systems.
3Reliability
If memory mapped access is implemented, then non-intrusive access to processor state is achieved, but interface complexity increases
Solution Approach 1:
The memory-mapped access interface is designed to handle multiple functions including trace data reading, configuration writing, and event trigger detection through a unified interface. This multi-functionality reduces the need for separate complex interfaces while maintaining reliable non-intrusive access.
Data Source
AI summary
In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.