Tri-Layer Patterning for Semiconductor Feature Transfer
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Solution Overview
Problem
The decreasing geometry sizes in semiconductor integrated circuits lead to manufacturing difficulties such as over etching or under etching in multi-layer patterning schemes, resulting in feature transfer failure and potential device failures.
Innovation Solution
A multiple layer scheme patterning method using a tri-layer structure with a pattern defining layer and an etch stop layer to promote etching selectivity, allowing for the transfer of features with desired profiles and dimensions into a material layer, and subsequent additional patterning processes to pattern the underlying film stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-layer patterning scheme is used to pattern layers in semiconductor processes, then functional density can be increased, but over etching or under etching occurs resulting in feature transfer failure
Solution Approach 1:
The patent divides the patterning process into multiple discrete steps using separate mandrel layers (first mandrel layer 104, second mandrel layer 106) and distinct etching operations. Each layer is patterned and transferred independently through controlled etching steps, preventing the cumulative errors that cause over-etching or under-etching in conventional multi-layer schemes. The segmentation of patterning operations allows precise control over feature transfer at each stage.
Solution Approach 2:
The patent introduces mandrel layers (104, 106) as intermediary structures that facilitate feature transfer without directly becoming part of the final device structure. These mandrel layers serve as temporary placeholders that define patterns during etching, then are removed after transferring the desired features. This intermediary approach enables precise pattern transfer while avoiding the etching control problems associated with direct multi-layer patterning.
2Manufacturing precision
If geometry sizes are decreased to increase functional density, then more circuits can be integrated, but manufacturing difficulties such as over etching or under etching increase
Solution Approach 1:
The patent performs preliminary patterning actions by forming mandrel layers (104, 106) with precise dimensions before the actual feature transfer etching. These mandrels are created with controlled thicknesses and patterns that pre-defin the final feature geometry. By establishing the pattern boundaries in advance through mandrel formation rather than direct etching, the process achieves better geometry size control even at reduced dimensions.
Solution Approach 2:
The patent utilizes parameter changes in the etching process by employing selective etching conditions for different mandrel layers and material stacks. Different etch selectivities, powers, and chemistries are applied to transfer features from mandrel layer 104 versus mandrel layer 106, enabling precise control over feature dimensions. This parameter optimization allows manufacturing of smaller geometries with reduced variability.
Data Source
AI summary
An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.