Tri-layer Spacers for Field-Effect Transistors
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Solution Overview
Problem
Existing spacer structures in field-effect transistors, particularly in FinFETs, face challenges in maintaining robustness and circuit speed due to the erosion of inner spacers, which can lead to unintended connections between the gate electrode and source/drain regions.
Innovation Solution
A tri-layer spacer structure is introduced, where the first spacer has a higher dielectric constant than the second spacer, and the second spacer has a higher dielectric constant than the third spacer, formed using atomic layer deposition (ALD) with specific gas phase reactants to achieve tailored dielectric constants and etch resistance, with the inner spacer being more susceptible to etching to prevent erosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a bi-layer spacer with inner spacer having lower dielectric constant is used to boost circuit speed, then circuit speed is improved, but the inner spacer becomes susceptible to erosion and loses robustness
Solution Approach 1:
The spacer is divided into three distinct layers (first, second, and third spacers) with different dielectric constants, where the second spacer with intermediate dielectric constant acts as a protective barrier between the high-speed inner spacer and the outer spacer, segmenting the protective function while maintaining circuit speed enhancement
Solution Approach 2:
The tri-layer spacer structure combines materials with different dielectric constants (first spacer: higher k, second spacer: intermediate k, third spacer: lower k) to create a composite structure that simultaneously achieves robust erosion resistance and high circuit speed performance, with each layer contributing specific properties to the overall system
2Reliability
If the outer spacer is designed to resist etching processes, then spacer robustness is improved, but the inner spacer may still erode and form voids linking gate electrode and source/drain regions
Solution Approach 1:
The second spacer with intermediate dielectric constant is positioned between the first and third spacers to serve as a cushioning layer that prevents complete erosion propagation, absorbing etching damage before it reaches the critical inner spacer region and maintaining spacer integrity throughout the process
3Reliability
If a tri-layer spacer structure with graded dielectric constants is implemented, then both robustness and circuit speed are enhanced, but the device complexity increases
Solution Approach 1:
Each spacer layer is assigned a specific dielectric constant tailored to its functional requirement: the first spacer has higher k for speed enhancement near the gate, the second spacer has intermediate k for balanced performance, and the third spacer has lower k for robustness, creating local quality optimization without excessive overall complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tri-layer spacer structure enhances the robustness and circuit speed by preventing spacer erosion, maintaining the separation between the gate electrode and source/drain regions, and allowing for lower threshold voltages and improved performance.
Implementation Method 1
The atomic layer deposition process includes adsorbing silicon on a surface of the gate electrode, adsorbing oxygen on the surface of the gate electrode, and, adsorbing carbon and nitrogen on the surface of the gate electrode after the oxygen is adsorbed on the surface of the gate electrode
Data Source
AI summary
Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.