Trim Circuit Latch Architecture for Multi-Mode Memory Calibration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional trim circuits for semiconductor memory devices face inefficiencies in calibrating trim codes, leading to variations in operating characteristics due to manufacturing variances, and existing test systems suffer from timing inefficiencies during parallel testing.
Innovation Solution
A trim circuit design that includes a trim code storage unit, a global latch unit, and a local latch unit, which calibrate and generate trim output signals by performing sequential latch operations, allowing for adaptive control of peripheral circuits and efficient calibration without altering stored trim codes, and a test system capable of performing parallel tests on multiple devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional trim circuits are used to calibrate trim codes, then manufacturing variances can be addressed, but calibration efficiency is reduced and adaptation to various operation modes is limited
Solution Approach 1:
The trim circuit is segmented into multiple latch units (first latch unit, second latch unit, third latch unit) that can independently hold different trim codes for different operation modes. This segmentation allows simultaneous storage of multiple calibrated trim codes, enabling efficient calibration across various operation modes without sequential processing delays.
Solution Approach 2:
The trim circuit is designed with multi-functional latch units that can store trim codes for multiple operation modes (read mode, program mode, erase mode) within the same circuit structure. This universal design allows the circuit to adapt to different operation modes by selecting appropriate latch units, improving both calibration efficiency and adaptability.
2Measurement precision
If trim codes are calibrated for different operation modes separately, then accurate calibration is achieved, but calibration time and complexity increase
Solution Approach 1:
Multiple latch units are pre-configured to store trim codes for different operation modes (read, program, erase) in advance. During calibration, the test apparatus can simultaneously program these pre-configured latch units with appropriate trim codes, eliminating the need for sequential calibration and reducing total calibration time while maintaining accuracy for each mode.
3Reliability
If manufacturing variances are compensated through trim circuit calibration, then device performance consistency is improved, but circuit complexity increases
Solution Approach 1:
Multiple latch units are merged into a single integrated trim circuit structure that shares common control logic and output pathways. This merging approach maintains device performance consistency by providing comprehensive trim code storage for all operation modes, while reducing overall circuit complexity compared to having separate calibration circuits for each mode.
Data Source
AI summary
A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.