Storage Controller Trim Completion Timing for I/O Performance
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Solution Overview
Problem
The input/output performance of flash memory-based storage devices is deteriorated due to the allocation of resources for processing trim commands, which are not efficiently managed, leading to over-occupancy of storage controller resources and degradation of read/write operations.
Innovation Solution
A storage controller with a trim performance manager that controls the transmission of trim command completions based on trim load values and namespace identifiers, using a trim performance control circuit and table to manage resource allocation and delay completion signals, thereby optimizing trim performance according to quality of service requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the storage controller processes trim commands with high priority, then trim operation speed is improved, but input/output performance deteriorates due to resource over-occupancy
Solution Approach 1:
The storage controller dynamically adjusts the transmission timing of completion signals for trim commands based on current system state and trim load values. Instead of fixed priority handling, the controller adaptively delays completion signal transmission to control the rate at which trim operations are issued, thereby preventing resource over-occupancy while maintaining acceptable trim performance
Solution Approach 2:
The controller changes the parameter of completion signal transmission timing based on trim load values and quality of service requirements. By adjusting when completion signals are sent back to the host, the controller effectively controls the throughput of trim commands, balancing trim operation speed with overall I/O performance
2Reliability
If more storage controller resources are allocated to trim command processing, then trim operation capability is improved, but read/write operation performance deteriorates
Solution Approach 1:
The storage controller ensures continuous processing of read/write operations while managing trim commands. By controlling the rate of trim command completion signal transmission, the controller maintains continuous useful action for data operations without interruption, while still making progress on trim operations through regulated completion signaling
Solution Approach 2:
The controller dynamically balances resource allocation between trim and data operations by adjusting completion signal transmission timing. This dynamic control allows the system to respond to changing workloads, ensuring that trim operations receive adequate resources without starving read/write operations
Data Source
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AI summary
According to an embodiment of present disclosure, a storage controller (110) configured to communicate with a host device (10) may be provided. The storage controller (110) may include a completion buffer that is configured to store one or more completions (CPLT), and transmit the one or more completions (CPLT) to the host device (10); a first core that is configured to generate a first completion and a first trim load value both corresponding to a first trim command received from the host device (10); and a trim performance control circuit that is configured to delay transmission of the first completion to the completion buffer based on the first trim load value, with the trim performance control circuit being connected to both the completion buffer and the first core.