Trim Register Parity Tracking for Latch Upset Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Latch upset events in memory devices can introduce errors into the trim data stored in trim registers, leading to incorrect indication of memory block usage, inefficient garbage collection, and reduced memory device performance.
Innovation Solution
Generating parity data using the trim data stored in the trim register, which can be a cyclic redundancy check (CRC), to track changes and detect latch upset events, and comparing this parity data with subsequently generated parity data to identify any discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If trim data is stored in trim registers to track memory block usage, then memory management efficiency is improved, but latch upset events can corrupt the trim data leading to incorrect memory block indication
Solution Approach 1:
The patent creates a copy of the trim data by generating parity data from the trim data stored in the trim register. This parity data serves as a backup reference that can be compared with subsequent reads of the trim data to detect latch upset events, thereby maintaining reliability without sacrificing memory management efficiency
Solution Approach 2:
The patent implements a feedback mechanism by periodically reading the trim data and comparing it with the previously generated parity data. This feedback loop detects changes in the trim data that indicate latch upset events, allowing the system to correct or respond to data corruption while maintaining efficient memory management operations
2Reliability
If parity data is generated and stored to detect latch upset events, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the parity data storage with the existing trim register structure by storing parity data in the same register or in closely associated storage locations. This integration approach provides data integrity protection without significantly increasing device complexity, as the parity functionality is combined with existing memory management infrastructure
Data Source
AI summary
Apparatuses, systems, and methods for tracking latch upset events using a trim register are described. An example method includes reading trim data from trim registers in a non-volatile memory device. The example method can further include generating parity data for the trim data. The example method can further include storing the parity data in the trim registers. The example method can further include, subsequent to the generation and storage of the parity data, re-reading the trim data from the trim registers, generating additional parity data, and comparing the parity data to the additional parity data.