Trim Registers for Flash Memory Access Accuracy
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Solution Overview
Problem
There is a need to improve the accuracy of memory access operations in flash memory devices, such as erase, read, and write operations, which are critical for maintaining data integrity and efficiency in electronic applications.
Innovation Solution
The implementation of a trim register array within memory devices that allows for the loading of customized trim settings during memory access operations, enabling adjustments to voltage settings and other parameters to enhance operation accuracy and reduce errors, particularly by associating specific trim settings with access operation commands and allowing for dynamic changes based on operational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If trim settings are loaded during memory access operations, then accuracy of memory access operations is improved, but device complexity increases
Solution Approach 1:
The patent divides the trim settings into separate trim registers that can be independently loaded and configured. Each trim register can be associated with specific memory access operations, allowing the system to manage complexity by segmenting the configuration process rather than handling all trim settings as a single complex unit.
Solution Approach 2:
The patent enables loading of trim settings before memory access operations are executed. By performing the trim register loading in advance (as a preliminary action), the actual memory access operations can proceed with optimized parameters already in place, improving accuracy without adding complexity during the critical access window.
2Measurement precision
If trim settings are adjusted in real-time, then operation accuracy is improved, but loss of time increases
Solution Approach 1:
The patent allows trim settings to be loaded into trim registers before the actual memory access operations begin. This preliminary loading of configuration data eliminates the need to pause or delay access operations for parameter adjustment, thereby maintaining high accuracy while minimizing time loss.
Solution Approach 2:
The patent enables the memory device to continue performing useful actions (memory access operations) while trim settings are being loaded into appropriate registers. By overlapping the trim loading process with other operational activities, the system maintains continuous productivity without significant time penalty for the accuracy-improving trim adjustments.
Data Source
AI summary
Memories include a controller that, in response to receiving a command to perform an access operation on an array of memory cells, might be configured to perform the access operation on the array of memory cells using trims corresponding to trim settings for the access operation. The controller, in response to receiving a command or a command sequence while performing the access operation that is indicative of a desire to suspend the access operation and load updated trim settings, might be further configured to suspend the access operation, load updated trim settings for the access operation into a particular trim register of a plurality of trim registers, set updated trims for the access operation in response to the updated trim settings in the particular trim register, and resume the access operation using the updated trims.