Trim Command Response Time Optimization in Memory Controllers
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Solution Overview
Problem
Current memory systems face challenges in shortening the response time for Trim commands, particularly when a wide range of logical block addresses (LBAs) are designated, leading to prolonged execution times and potential delays in processing subsequent commands.
Innovation Solution
The memory system employs a hierarchical structure for its address translation table (LUT) and valid data map (ADM), where the LUT is updated before transmitting a response to the Trim command, and the ADM update is delayed by storing invalidation requests in a queue, allowing for faster response times and minimizing delays in processing other commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the address translation table (LUT) and valid data map (ADM) are updated sequentially when a Trim command is received, then data consistency is maintained, but the response time for the Trim command increases
Solution Approach 1:
The patent segments the update process into two independent parts: LUT update and ADM update. The LUT is updated first and can be completed independently, while the ADM update is deferred to a later time. This segmentation allows the system to return a Trim command response after the critical LUT update without waiting for the ADM update, thereby reducing response time while maintaining data consistency through the use of a update queue.
Solution Approach 2:
The patent performs the LUT update as a preliminary action before returning the Trim command response. By completing the LUT update first, the system ensures that the address translation information is current and consistent, which is critical for subsequent read/write operations. The ADM update is then performed later using preliminary queued information, allowing the response to be returned faster while still maintaining eventual consistency.
2Reliability
If the valid data map (ADM) is updated immediately upon receiving a Trim command, then data validity information is kept current, but processing delays affect subsequent command handling
Solution Approach 1:
The patent performs the ADM update as a preliminary queued action that occurs after the Trim command response is sent. The update information is captured and queued first, then the ADM is updated later using this queued information. This allows the system to maintain accurate tracking of invalidation requests while not blocking the response path, thereby improving command processing throughput without completely sacrificing data validity accuracy.
Solution Approach 2:
The patent introduces an update queue as an intermediary between the Trim command reception and the ADM update execution. This queue stores the invalidation information temporarily, allowing the system to acknowledge the Trim command quickly while still processing the ADM update in the background. The intermediary queue decouples the response time from the update time, improving throughput while maintaining eventual consistency.
3Reliability
If a wide range of logical block addresses (LBAs) is designated in a Trim command, then data invalidation coverage is improved, but the execution time and system load increase significantly
Solution Approach 1:
The patent segments the ADM update process into manageable units that are processed from a queue. When a Trim command with a wide LBA range is received, the invalidation information is divided into multiple update entries in the queue, which are then processed incrementally. This segmentation prevents a single large Trim command from blocking the entire system, allowing the response to be returned quickly while the comprehensive invalidation coverage is achieved progressively through queued updates.
Data Source
AI summary
According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.