Trimmed Source/Drain Epitaxy for Lower Parasitic Capacitance
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Solution Overview
Problem
In the semiconductor industry, as devices approach sub-10 nanometer technology nodes, parasitic capacitance from source/drain epitaxial features increases resistance-capacitance response time and deteriorates circuit performance, especially in high-speed circuits, and existing manufacturing methods fail to adequately prevent adjacent epitaxial features from merging, leading to higher parasitic capacitance and leakage issues.
Innovation Solution
The method involves reshaping source/drain epitaxial features to reduce their volume and increase the lateral distance between adjacent features, thereby reducing parasitic capacitance and suppressing leakage current, by modifying their profile through a selective etching process that trims down the width and height of the epitaxial features, ensuring they do not merge and maintaining a sufficient aspect ratio to minimize resistance while reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain epitaxial features are grown with large volumes to reduce resistance, then electrical conductivity is improved, but parasitic capacitance increases and RC response time deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the geometric dimensions of epitaxial features through selective etching. The width and height of the epitaxial features are reduced from their original grown dimensions, changing the physical parameters to achieve optimal balance between resistance and capacitance. This is accomplished by controlling etch depth and duration to achieve target dimensions that minimize RC time constant while maintaining adequate conductivity.
2Ease of manufacture
If adjacent source/drain epitaxial features are allowed to merge to fill spacing, then manufacturing complexity is reduced, but parasitic capacitance increases and leakage current worsens
Solution Approach 1:
The patent applies preliminary action by performing selective etching on epitaxial features before final device assembly and interconnection steps. The etching process pre-shapes the epitaxial features to appropriate dimensions and spacing, preventing merging before it occurs. This preliminary dimension control ensures that adjacent features remain properly separated throughout subsequent manufacturing steps, avoiding leakage paths while maintaining manufacturing efficiency.
3Object-generated harmful factors
If epitaxial features are trimmed to reduce volume and prevent merging, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent introduces an intermediary selective etching process between epitaxial growth and final device assembly. This intermediary step serves as a mediator that adjusts the dimensions of epitaxial features to optimal values. The etching process acts as a controllable intermediate transformation that converts oversized epitaxial features into properly dimensioned structures, achieving capacitance reduction without requiring complete process redesign.
4Reliability
If epitaxial features are grown to maintain aspect ratio for low resistance, then electrical performance is improved, but leakage between contacts and gate stacks increases
Solution Approach 1:
The patent applies parameter changes by selectively reducing the horizontal dimensions (width) of epitaxial features while preserving their vertical height. This differential dimension control changes the aspect ratio parameters to achieve optimal electrical performance. The selective etching process modifies width more than height, maintaining sufficient aspect ratio for low resistance contact while reducing lateral extent to prevent leakage paths to gate stacks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhances circuit performance by improving the RC response time, and prevents adjacent epitaxial features from merging, thus maintaining device efficiency and performance in high-speed applications.
Implementation Method 1
by modifying their profile through a selective etching process that trims down the width and height of the epitaxial features
Data Source
AI summary
A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing an epitaxial feature in the recess to fully covers an end of the semiconductor fin that is otherwise exposed in the recess, trimming the epitaxial feature to reduce a width of the epitaxial feature to expose again a portion of the end of the semiconductor fin in the recess, depositing a dielectric layer on the epitaxial feature and in physical contact with the exposed portion of the end of the semiconductor fin, and replacing the dummy gate structure with a metal gate structure.