Trimmed GAA Channels for Work Function Metal and Threshold Control
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Solution Overview
Problem
In gate-all-around (GAA) semiconductor devices, the thick gate interfacial layer in the input/output (I/O) area limits the space between channel semiconductor layers, preventing the formation of a work function metal layer and merging high-k dielectric layers, which results in an undesirably high threshold voltage and degraded performance.
Innovation Solution
The channel semiconductor layers in the I/O area are trimmed to be thinner than those in the core area, enlarging the space between them, allowing for the formation of a work function metal layer and enabling dipole processing of the high-k dielectric layer to achieve the desired threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate interfacial layer is made thick to ensure proper interface quality, then the interface reliability is improved, but the space between channel semiconductor layers is reduced, preventing work function metal layer formation
Solution Approach 1:
The gate structure is segmented into multiple functional layers: gate interfacial layer, high-k dielectric layer, and work function metal layer. Each layer performs a specific function, allowing the thick interfacial layer to maintain reliability while separate spaces are allocated for other components through vertical stacking and regional differentiation.
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional gate-all-around structure with vertical stacking of multiple layers. This dimensional change creates additional vertical space and allows the thick interfacial layer to coexist with other necessary layers through vertical arrangement rather than competing for horizontal space.
2Reliability
If the high-k dielectric layer is made thick to achieve desired capacitance, then the gate control is improved, but the layers merge between channel semiconductor layers, eliminating work function metal formation space
Solution Approach 1:
The gate dielectric system is segmented into a thick high-k dielectric layer for capacitance and gate control, combined with a separate work function metal layer for threshold voltage adjustment. This segmentation allows each component to be optimized independently while maintaining proper spacing through the gate-all-around vertical structure.
Solution Approach 2:
The gate structure uses a composite of multiple materials with different functions: high-k dielectric material for electrical capacitance and work function metal material for threshold voltage control. This composite approach allows the system to achieve both high gate control and proper threshold voltage without layer merging.
3Reliability
If the work function metal layer is added to control threshold voltage, then the device performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The gate structure is segmented into distinct functional layers that can be deposited and processed separately using standard semiconductor fabrication techniques. The work function metal layer is deposited as a separate step after the high-k dielectric, allowing independent optimization and simplifying the overall manufacturing process despite the added functionality.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.