Trimmed Nanosheet Channels for Low-Resistance Backside Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for fabricating nanosheet transistors with direct backside contacts face challenges such as excessive placeholder erosion during substrate removal, leading to reduced cross-sectional dimensions and increased contact resistance.
Innovation Solution
A method involving selective etching and trimming of channel nanosheets to maintain suitable dimensions, followed by forming backside contacts that are self-aligned to shallow trench isolation regions, ensuring proper contact resistance is maintained.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used for fabricating nanosheet transistors with direct backside contacts, then the fabrication process is simplified, but excessive placeholder erosion occurs during substrate removal leading to reduced cross-sectional dimensions and increased contact resistance
Solution Approach 1:
The patent applies preliminary action by forming a trim mask pattern before substrate removal to pre-defend the placeholder regions. This proactive measure prevents excessive erosion by establishing protective boundaries in advance, ensuring that the placeholder cross-sectional dimensions are maintained throughout the substrate removal process without requiring complex in-situ control mechanisms.
2Device complexity
If conventional fabrication methods are used, then the process steps are reduced, but contact resistance increases due to reduced cross-sectional dimensions from placeholder erosion
Solution Approach 1:
The trim mask pattern is formed in advance to proactively prevent placeholder erosion. This preliminary protective structure ensures that the placeholder cross-sectional dimensions remain sufficient to maintain low contact resistance, addressing the reliability concern without adding significant process complexity.
Solution Approach 2:
The trim mask pattern acts as an intermediary protective layer between the etching process and the placeholder regions. This intermediate structure mediates the interaction by providing a sacrificial barrier that prevents direct erosion of the placeholders, thereby preserving their dimensions and ensuring low contact resistance.
3Reliability
If placeholder dimensions are increased to prevent erosion, then contact resistance is reduced, but the device footprint increases
Solution Approach 1:
By forming the trim mask pattern in advance, the patent enables precise definition of placeholder boundaries before erosion occurs. This allows the use of smaller placeholder dimensions while still preventing excessive erosion, thereby maintaining low contact resistance without increasing the device footprint.
Data Source
AI summary
A nanosheet semiconductor structure including a plurality of channel nanosheets arranged one above another and each surrounded by a gate structure, where a width of each channel region of the plurality of channel nanosheets varies across its length.


